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参数资料
| 型号： | DR-TRC105-304-EV |
| 厂商： | RFM |
| 文件页数： | 60/67页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION 304MHZ RFM RFIC |
| 标准包装： | 1 |
| 类型： | 收发器 |
| 频率： | 303.325MHz ~ 307.3MHz |
| 适用于相关产品： | TRC105 |
| 已供物品： | 2 个板，天线，电池 |
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Recognition of start pattern in receive mode
Automatic removal of preamble and start pattern in receive mode (payload only in FIFO)
Flagging of received packets with errors or flagging and discard of packets with errors
Filtering of received packets based on address byte - address match only, address byte plus 0x00 broad-
cast address or address byte plus 0x00 and 0xFF broadcast addresses
New IRQ0 and IRQ1 mapping options
The SPI interface is used with Packet data mode as with Buffered data mode. IRQ0 and IRQ1 mapping is config-
ured in register IRQCFG0D . Bits 7..6 select the signal for IRQ0 in the receive mode. In transmit mode, IRQ0
mapping is set by IRQCFG0D bit 3. IRQCFG0D bits 5..4 select the signal for IRQ1 in the receive mode. Bit 3 se-
lects the IRQ1 signal in transmit mode. The mapping options for Packet data mode are summarized in Table 81
below:
IRQCFG0D bits
7..6
7..6
7..6
7..6
3
3
5..4
5..4
5..4
5..4
3
3
Cfg
00
01
10
11
1
0
00
01
10
11
0
1
State
RX
RX
RX
RX
TX
TX
RX
RX
RX
RX
TX
TX
IRQ
0
0
0
0
0
0
1
1
1
1
1
1
Source
Data_Rdy (CRC OK)
Write_byte (high pulse when received byte written to FIFO)
nFIFOEMPY (low when FIFO is empty)
Start Pattern Detect or Node Address Match
FIFO_Int_Tx
nFIFOEMPY
CRC_OK
FIFOFULL
RSSI_IRQ
FIFO_Int_Rx
FIFOFULL
TX_Stop
Table 81
In addition, IRQCFG0E allows several internal interrupts to be configured. See Table 82 below:
IRQCFG0E bits
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Cfg
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
Internal Interrupt Control
Start FIFO fill when start pattern detected
Control FIFO with bit 6
Stop filling FIFO (if bit 7 is 0, this is Start Pattern Detect)
Start filling FIFO
Transmitting all pending bits in FIFO
All bits in FIFO transmitted
FIFO OK
FIFO overflow (write 1 to reset FIFO)
Disable RSSI interrupt (bit 2)
Enable RSSI interrupt (bit 2)
RF signal ≥ RSSI threshold
RF signal < RSSI Threshold
PLL not locked
PLL locked
PLL_LOCK signal disabled (bit 1 above), Pin 23 set high
PLL_LOCK signal enabled
Table 82
www.RFM.com E-mail: info@rfm.com
? 2009-2013 by RF Monolithics, Inc.
Technical support +1.800.704.6079
Page 60 of 67
TRC105 - 05/29/13
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