参数资料
型号: DS1075M-60
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: XO, clock
英文描述: 60 MHz, OTHER CLOCK GENERATOR, PDIP8
封装: 0.300 INCH, DIP-8
文件页数: 14/18页
文件大小: 251K
代理商: DS1075M-60
DS1075
5 of 18
Table 2
DIV1
BIT
E/ I
BIT*
MSEL
BIT
M
BIT
OPERATION
0000
INTERNAL OSCILLATOR DIVIDED BY 4*N
0001
INTERNAL OSCILLATOR DIVIDED BY 2*N
0
1
X
INTERNAL OSCILLATOR DIVIDED BY N
0
1
X
EXTERNAL OSCILLATOR DIVIDED BY N
1
0
X
INTERNAL OSCILLATOR DIVIDED BY 1
1
X
EXTERNAL OSCILLATOR DIVIDED BY 1
*Assuming PDN bit = 1, otherwise internal/external selection will be controlled by the PDN / SELX pin.
DIV WORD Figure 3
(MSB)
(LSB)
N (9-BITS)
PDN
This bit is used to determine the function of the PDN / SELX pin. If PDN=0, the PDN / SELX pin can be
used to determine the timing reference (either the internal oscillator or an external reference/crystal). If
PDN=1, the PDN /SELX pin is used to put the device into power-down mode.
EN0
This bit is used to determine whether the OUT0 pin is active or not. If EN0 =1, OUT0 is disabled (High-
impedance). If EN0 =0, the internal reference clock (MCLK) is output from OUT0. The OE pin has no
effect on OUT0, but OUT0 is disabled as part of the power-down sequence.
N
These nine bits determine the value of the programmable divider. The range of divisor values is from 2 to
513, and is equal to the programmed value of N plus 2:
Table 3
BIT
VALUES
DIVISOR (N)
VALUE
000000000
2
000000001
3
..
111111111
513
NOTE:
The maximum value of N is constrained by the minimum output frequency. If the internal clock is
selected, INTOSC/(M*N) must be greater than fOUTmin; if the external clock is selected, EXTCLK/N must
be greater than fOUTmin . (If DIV1=1, then INTOSC or EXTCLK, as applicable, must exceed fOUTmin).
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