参数资料
型号: DS1077Z-100
厂商: DALLAS SEMICONDUCTOR
元件分类: Clock Generator
英文描述: 100 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 0.150 INCH, SOIC-8
文件页数: 11/17页
文件大小: 103K
代理商: DS1077Z-100
DS1077
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OVERVIEW
A block diagram of the DS1077 is shown in Figure 1. The DS1077 consists of four major components:
Internal Master Oscillator
Prescalers
Programmable Divider
Control Registers
The Internal Oscillator is factory trimmed to provide a master frequency (Master Clk) that can be
routed directly to the outputs (OUT0 & OUT1) or through separate PRESCALERS (P0 & P1). OUT1 can
also be routed through an additional DIVIDER (N).
The Prescaler (P0) divides the Master Clock by 1,2,4, or 8 to be routed directly to the OUT0 pin.
The Prescaler (P1) divides the Master Clock by 1,2,4, or 8 that can be routed directly to the OUT1 pin or
to the Divider (N) input, which is then routed to the OUT1 pin.
The Programmable Divider (N) divides the Prescaler Output (P1) by any number selected between 2 and
1025 to provide the Main Output ( OUT1) or it can be bypassed altogether by use of the DIV1 register bit.
The value of N is stored in the N register.
The Control Registers are user-programmable through a 2-wire serial interface to determine operating
frequency (values of P0, P1 & N) and modes of operation. The register values are stored in EEPROM and
therefore only need to be programmed to alter frequencies and operating modes.
PIN DESCRIPTIONS
OUTPUT 1 (OUT1) This pin is the main oscillator output; its frequency is determined by the control
register settings for the prescaler P1 (mode bits 1M1 & 1M0) and divider N (DIV WORD).
OUTPUT 0 (OUT0) A reference output, OUT0, is taken from the output of the reference select mux. Its
frequency is determined by the control register settings for CTRL0 and values of Prescaler P0 (mode bits
0M1 & 0M0). (Refer to Table 1)
CONTROL PIN 0 (CTRL0) A multi-functional input pin that can be selected as a MUX SELECT,
OUTPUT ENABLE and/or a POWER DOWN. Its function is determined by the user-programmable
control register values EN0, SEL0 and PDN0. (Refer to Table 1)
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