参数资料
型号: DS1077Z-100
厂商: DALLAS SEMICONDUCTOR
元件分类: Clock Generator
英文描述: 100 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 0.150 INCH, SOIC-8
文件页数: 9/17页
文件大小: 103K
代理商: DS1077Z-100
DS1077
17 of 17
8. A fast mode device can be used in a standard mode system, but the requirement tSU:DAT >250ns must
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line tR MAX+tSU:DAT = 1000+250 = 1250ns before the SCL line is released.
9. Cb - total capacitance of one bus line in pF.
TIMING DIAGRAM
SU:STO
t
SP
HD:STA
t
t SU:STA
SU:DAT
t
tHIGH
R
t
LOW
tHD:STA
SCL
START
SDA
STOP
t
BUF
tF
REPEATED
START
tHD:DAT
ORDERING INFORMATION
Example:
DS1077Z-100
DS1077
Z=
SOIC
U=
uSOP
133 = 133.333 MHz
125 = 125.000 MHz
120 = 120.000 MHz
100 = 100.000 MHz
66 = 66.666 MHz
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相关代理商/技术参数
参数描述
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