参数资料
型号: DS1077Z-100
厂商: DALLAS SEMICONDUCTOR
元件分类: Clock Generator
英文描述: 100 MHz, OTHER CLOCK GENERATOR, PDSO8
封装: 0.150 INCH, SOIC-8
文件页数: 8/17页
文件大小: 103K
代理商: DS1077Z-100
DS1077
16 of 17
AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE
(0
°°°°C to +70°°°°C, 4.5V ≤≤≤≤ V
DD
≤≤≤≤ 5.25V)
PARAMETER
SYMBOL
CONDITION
MIN
TYP
MAX
UNITS
NOTES
SCL clock frequency
fSCL
Fast Mode
400
kHz
Standard Mode
100
Bus free time between
tBUF
Fast Mode
1.3
s
a STOP and START
condition
Standard Mode
4.7
Hold time (repeated)
tHD:STA
Fast Mode
0.6
s
6
START condition.
Standard Mode
4.0
LOW period of SCL
tLOW
Fast Mode
1.3
s
Standard Mode
4.7
HIGH period of SCL
tHIGH
Fast Mode
0.6
s
Standard Mode
4.0
Set-up time for a
tSU:STA
Fast Mode
0.6
s
Repeated START
Standard Mode
4.7
Data hold time
tHD:DAT
Fast Mode
0
0.9
s
7,8
Standard Mode
0
Data set-up time
tSU:DAT
Fast Mode
100
ns
Standard Mode
250
Rise time of both SDA
tR
Fast Mode
20+
0.1CB
300
ns
9
And SCL signals
Standard Mode
1000
Fall time of both SDA
tF
Fast Mode
20+
0.1CB
300
ns
9
And SCL signals
Standard Mode
Set-up time for STOP
tSU:STO
Fast Mode
0.6
s
Standard Mode
4.0
Capacitive load for each
bus line
Cb
400
pF
9
Input Capacitance
CI
5pF
NOTES:
1. All voltages are referenced to ground.
2. 8.05KHz is obtained from a –66MHz std part
3. PDN is a power down signal applied to either CTRL0 or CTRL1 pins as appropriate
4. Output voltage swings may be impaired at high frequencies combined with high output loading
5. After this period, the first clock pulse is generated.
6. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIH
MIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
7. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
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