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参数资料
| 型号： | DS1230AB |
| 厂商： | DALLAS SEMICONDUCTOR |
| 元件分类： | DRAM |
| 英文描述： | 256K NV SRAM(256K非易失性SRAM) |
| 中文描述： | 32K X 8 NON-VOLATILE SRAM MODULE, 200 ns, DMA28 |
| 文件页数： | 2/12页 |
| 文件大小： | 120K |
| 代理商： | DS1230AB |
DS1230Y/AB
042398 2/12
DESCRIPTION
The DS1230 256K Nonvolatile SRAMs are 262,144–bit,
fully static, nonvolatile SRAMs organized as 32,768
words by 8 bits. Each NV SRAM has a self–contained
lithium energy source and control circuitry which con-
stantly monitors V
CC
for an out–of–tolerance condition.
When such a condition occurs, the lithium energy
source is automatically switched on and write protection
is unconditionally enabled to prevent data corruption.
DIP-package DS1230 devices can be used in place of
existing 32K x 8 static RAMs directly conforming to the
popular bytewide 28–pin DIP standard. The DIP
devices also match the pinout of 28256 EEPROMs, al-
lowing direct substitution while enhancing performance.
DS1230 devices in the Low Profile Module package are
specifically designed for surface–mount applications.
There is no limit on the number of write cycles that can
be executed and no additional support circuitry is re-
quired for microprocessor interfacing.
READ MODE
The DS1230 devices execute a read cycle whenever
WE (Write Enable) is inactive (high) and CE (Chip En-
able) and OE (Output Enable) are active (low). The
unique address specified by the 15 address inputs (A
0
-
A
14
) defines which of the 32,768 bytes of data is to be
accessed. Valid data will be available to the eight data
output drivers within t
ACC
(Access Time) after the last
address input signal is stable, providing that CE and OE
(Output Enable) access times are also satisfied. If OE
and CE access times are not satisfied, then data access
must be measured from the later occurring signal (CE or
OE) and the limiting parameter is either t
CO
for CE or t
OE
for OE rather than address access.
WRITE MODE
The DS1230 devices execute a write cycle whenever
the WE and CE signals are active (low) after address in-
puts are stable. The later occurring falling edge of CE or
WE will determine the start of the write cycle. The write
cycle is terminated by the earlier rising edge of CE or
WE. All address inputs must be kept valid throughout
the write cycle. WE must return to the high state for a
minimum recovery time (t
WR
) before another cycle can
be initiated. The OE control signal should be kept inac-
tive (high) during write cycles to avoid bus contention.
However, if the output drivers are enabled (CE and OE
active) then WE will disable the outputs in t
ODW
from its
falling edge.
DATA RETENTION MODE
The DS1230AB provides full functional capability for
V
CC
greater than 4.75 volts and write protects by 4.5
volts. The DS1230Y provides full functional capability
for V
CC
greater than 4.5 volts and write protects by 4.25
volts. Data is maintained in the absence of V
CC
without
any additional support circuitry. The nonvolatile static
RAMs constantly monitor V
CC
. Should the supply volt-
age decay, the NV SRAMs automatically write protect
themselves, all inputs become “don’t care,” and all out-
puts become high impedance. As V
CC
falls below ap-
proximately 3.0 volts, a power switching circuit con-
nects the lithium energy source to RAM to retain data.
During power–up, when V
CC
rises above approximately
3.0 volts, the power switching circuit connects external
V
CC
to RAM and disconnects the lithium energy source.
Normal RAM operation can resume after V
CC
exceeds
4.75 volts for the DS1230AB and 4.5 volts for the
DS1230Y.
FRESHNESS SEAL
Each DS1230 device is shipped from Dallas Semicon-
ductor with its lithium energy source disconnected,
guaranteeing full energy capacity. When V
CC
is first
applied at a level greater than 4.25 volts, the lithium en-
ergy source is enabled for battery back–up operation.
PACKAGES
The DS1230 devices are available in two packages:
28–pin DIP and 34–pin PowerCap Module (PCM). The
28–pin DIP integrates a lithium battery, an SRAM
memory and a nonvolatile control function into a single
package with a JEDEC–standard 600 mil DIP pinout.
The 34–pin PowerCap Module integrates SRAM
memory and nonvolatile control along with contacts for
connection to the lithium battery in the DS9034PC Pow-
erCap. The PowerCap Module package design allows
a DS1230 PCM device to be surface mounted without
subjecting its lithium backup battery to destructive high–
temperature reflow soldering. After a DS1230 PCM is
reflow soldered, a DS9034PC PowerCap is snapped on
top of the PCM to form a complete Nonvolatile SRAM
module. The DS9034PC is keyed to prevent improper
attachment. DS1230 PowerCap Modules and
DS9034PC PowerCaps are ordered separately and
shipped in separate containers. See the DS9034PC
data sheet for further information.
相关PDF资料 |
PDF描述 |
|---|---|
| DS1231 | Power Monitor Chip(电源监控芯片) |
| DS1231S | Power Monitor Chip(电源监控芯片) |
| DS1232LP(中文) | Low Power MicroMonitor Chip(低功耗微监控芯片) |
| DS1232LPS(中文) | Low Power MicroMonitor Chip(低功耗微监控芯片) |
| DS1232LP | Low Power MicroMonitor Chip(低功耗微监控芯片) |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS1230AB-100 | 功能描述:NVRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1230AB-100+ | 功能描述:NVRAM 256k Nonvolatile SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
| DS1230AB-100IND | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:256k Nonvolatile SRAM |
| DS1230AB-100-IND | 制造商:未知厂家 制造商全称:未知厂家 功能描述:NVRAM (Battery Based) |
| DS1230AB-120 | 功能描述:NVRAM 256k Nonvolatile SRAM RoHS:否 制造商:Maxim Integrated 数据总线宽度:8 bit 存储容量:1024 Kbit 组织:128 K x 8 接口类型:Parallel 访问时间:70 ns 电源电压-最大:5.5 V 电源电压-最小:4.5 V 工作电流:85 mA 最大工作温度:+ 70 C 最小工作温度:0 C 封装 / 箱体:EDIP 封装:Tube |
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