参数资料
型号: DS1689SN+T&R
厂商: Maxim Integrated Products
文件页数: 15/36页
文件大小: 0K
描述: IC RTC SER NV RAM CTRL IN 28SOIC
标准包装: 1,000
类型: 时钟/日历
特点: NVSRAM
存储容量: 114B
时间格式: HH:MM:SS(12/24 小时)
数据格式: YY-MM-DD-dd
接口: 并联
电源电压: 2.7 V ~ 3.3 V,4.5 V ~ 5.5 V
电压 - 电源,电池: 2.5 V ~ 3.7 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC
包装: 带卷 (TR)
DS1689/DS1693
22 of 36
Extended Control Register 4B
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
ABE
E32K
CS
RCE
PRS
RIE
WIE
KSE
Bit 7: ABE (Auxiliary Battery Enable). This bit, when written to logic 1, enables the VBAUX pin for
extended functions.
Bit 6: E32K (Enable 32.768kHz Output). This bit, when written to logic 1, enables the 32,768Hz
oscillator frequency to be output on the SQW pin provided SQWE = 1.
Bit 5: CS (Crystal Select). When CS is set to 0, the oscillator is configured for operation with a crystal
that has a 6pF specified load capacitance. When CS = 1, the oscillator is configured for a 12.5pF crystal.
Bit 4: RCE (RAM Clear Enable). When set to a 1, this bit enables a low level on pin 4 (
RCLR) to clear
all 114 bytes of user RAM. When RCE = 0, the RAM clear function is disabled.
Bit 3: PRS (PAB Reset Select). When set to 0 the
PWR pin is set high impedance when the DS1689
goes into power-fail. When set to 1, the
PWR pin remains active upon entering power-fail.
Bit 2: RIE (RAM Clear Interrupt Enable). When RIE is set to 1, the
IRQ pin is driven low when a
RAM clear function is completed.
Bit 1: WIE (Wake-Up Alarm Interrupt Enable). When VCC voltage is absent and WIE is set to 1, the
PWR pin is driven active low when a wake-up condition occurs, causing the WF bit to be set to 1. When
VCC is then applied, the IRQ pin is also driven low. If WIE is set while system power is applied, both IRQ
and
PWR are driven low in response to WF being set to 1. When WIE is cleared to 0, the WF bit has no
effect on the
PWR or IRQ pins.
Bit 0: KSE (Kickstart Interrupt Enable). When VCC voltage is absent and KSE is set to 1, the PWR pin
is driven active low when a kickstart condition occurs (
KS pulsed low), causing the KF bit to be set to 1.
When VCC is then applied, the IRQ pin is also driven low. If KSE is set to 1 while system power is
applied, both
IRQ and PWR are driven low in response to KF being set to 1. When KSE is cleared to 0,
the KF bit has no effect on the
PWR or IRQ pins.
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