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参数资料
| 型号： | DS1689SN+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 6/36页 |
| 文件大小： | 0K |
| 描述： | IC RTC SER NV RAM CTRL IN 28SOIC |
| 标准包装： | 1,000 |
| 类型： | 时钟/日历 |
| 特点： | NVSRAM |
| 存储容量： | 114B |
| 时间格式： | HH:MM:SS（12/24 小时） |
| 数据格式： | YY-MM-DD-dd |
| 接口： | 并联 |
| 电源电压： | 2.7 V ~ 3.3 V，4.5 V ~ 5.5 V |
| 电压 - 电源，电池： | 2.5 V ~ 3.7 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC |
| 包装： | 带卷 (TR) |
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DS1689/DS1693
14 of 36
REGISTER B
MSB
LSB
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SET
PIE
AIE
UIE
SQWE
DM
24/12
DSE
Bit 7: SET. When the SET bit is 0, the update transfer functions normally by advancing the counts once
per second. When the SET bit is written to 1, any update transfer is inhibited and the program can
initialize the time and calendar bytes without an update occurring in the midst of initializing. Read cycles
can be executed in a similar manner. SET is a read/write bit that is not modified by internal functions of
the DS1689/DS1693.
Bit 6: PIE (Periodic Interrupt Enable). This bit is a read/write bit that allows the periodic interrupt flag
(PF) bit in Register C to drive the
IRQ pin low. When the PIE bit is set to 1, periodic interrupts are
generated by driving the
IRQ pin low at a rate specified by the RS3–RS0 bits of Register A. A 0 in the
PIE bit blocks the
IRQ output from being driven by a periodic interrupt, but the periodic flag (PF) bit is
still set at the periodic rate. PIE is not modified by any internal DS1689/DS1693 functions.
Bit 5: AIE (Alarm Interrupt Enable). This bit is a read/write bit which, when set to 1, permits the alarm
flag (AF) bit in Register C to assert
IRQ. An alarm interrupt occurs for each second that the three time
bytes equal the three alarm bytes, including a don’t care alarm code of binary 11XXXXXX. When the
AIE bit is set to 0, the AF bit does not initiate the
IRQ signal. The internal functions of the
DS1689/DS1693 do not affect the AIE bit.
Bit 4: UIE (Update-Ended Interrupt Enable). This bit is a read/write that enables the update-end flag
(UF) bit in Register C to assert
IRQ. The SET bit going high clears the UIE bit.
Bit 3: SQWE (Square-Wave Enable). When this bit is set to 1, a square-wave signal at the frequency
set by the rate-selection bits RS3–RS0 and the E32K bit is driven out on the SQW pin. When the SQWE
bit is set to 0, the SQW pin is held low. SQWE is a read/write bit.
Bit 2: DM (Data Mode). This bit indicates whether time and calendar information is in binary or BCD
format. The DM bit is set by the program to the appropriate format and can be read as required. This bit is
not modified by internal functions. A 1 in DM signifies binary data while a 0 in DM specifies Binary
Coded Decimal (BCD) data.
Bit 1: 24/12 (24/12 Control Bit). This bit establishes the format of the hours byte. A 1 indicates the 24-
hour mode and a 0 indicates the 12-hour mode. This bit is read/write.
Bit 0: DSE (Daylight Saving Enable). This bit is a read/write bit which enables two special updates
when DSE is set to 1. On the first Sunday in April the time increments from 1:59:59 am to 3:00:00 AM.
On the last Sunday in October when the time first reaches 1:59:59 AM it changes to 1:00:00 AM. These
special updates do not occur when the DSE bit is 0. This bit is not affected by internal functions.
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相关代理商/技术参数 |
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| DS1689S-TRL | 功能描述:IC RTC SER W/NV RAM CTRL 28-SOIC RoHS:否 类别:集成电路 (IC) >> 时钟/计时 - 实时时钟 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- 类型:时钟/日历 特点:警报器，闰年，SRAM 存储容量:- 时间格式:HH:MM:SS（12/24 小时） 数据格式:YY-MM-DD-dd 接口:SPI 电源电压:2 V ~ 5.5 V 电压 - 电源，电池:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-WDFN 裸露焊盘 供应商设备封装:8-TDFN EP 包装:管件 |
| DS1691 | 功能描述:实时时钟 RoHS:否 制造商:Microchip Technology 功能:Clock, Calendar. Alarm RTC 总线接口:I2C 日期格式:DW:DM:M:Y 时间格式:HH:MM:SS RTC 存储容量:64 B 电源电压-最大:5.5 V 电源电压-最小:1.8 V 最大工作温度:+ 85 C 最小工作温度: 安装风格:Through Hole 封装 / 箱体:PDIP-8 封装:Tube |
| DS1691 WAF | 制造商:Texas Instruments 功能描述: |
| DS1691/1692 WAF | 制造商:Texas Instruments 功能描述: |
| DS1691A | 制造商:NSC 制造商全称:National Semiconductor 功能描述:(RS-422/RS-423) Line Drivers with TRI-STATE Outputs |
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