参数资料
型号: DS1689SN+T&R
厂商: Maxim Integrated Products
文件页数: 36/36页
文件大小: 0K
描述: IC RTC SER NV RAM CTRL IN 28SOIC
标准包装: 1,000
类型: 时钟/日历
特点: NVSRAM
存储容量: 114B
时间格式: HH:MM:SS(12/24 小时)
数据格式: YY-MM-DD-dd
接口: 并联
电源电压: 2.7 V ~ 3.3 V,4.5 V ~ 5.5 V
电压 - 电源,电池: 2.5 V ~ 3.7 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
供应商设备封装: 28-SOIC
包装: 带卷 (TR)
DS1689/DS1693
9 of 36
minute with “don’t care” codes in the hours and minute alarm bytes. The “don’t care” codes in all three
alarm bytes create an interrupt every second. The three alarm bytes may be used in conjunction with the
date alarm as described in the Wakeup/Kickstart section. The century counter will be discussed later in
this text.
Table 1. Time, Calendar, and Alarm Data Modes
RANGE
ADDRESS
LOCATION
FUNCTION
DECIMAL
RANGE
BINARY DATA
MODE
BCD DATA
MODE
00H
Seconds
0-59
00-3B
00-59
01H
Seconds Alarm
0-59
00-3B
00-59
02H
Minutes
0-59
00-3B
00-59
03H
Minutes Alarm
0-59
00-3B
00-59
Hours 12-hr Mode
1-12
01-0C AM, 81-8C PM
01-12 AM, 81-92 PM
04H
Hours 24-hr Mode
0-23
00-17
00-23
Hours Alarm 12-hr
Mode
1-12
01-0C AM, 81-8C PM
01-12 AM, 81-92 PM
05H
Hours Alarm 24-hr
Mode
0-23
00-17
00-23
06H
Day of Week
Sunday=1
1-7
01-07
07H
Date of Month
1-31
01-1F
01-31
08H
Month
1-12
01-0C
01-12
09H
Year
0-99
00-63
00-99
BANK1, 48H
Century
0-99
00-63
00-99
BANK 1, 49H
Date Alarm
1-31
01-1F
01-31
CONTROL REGISTERS
The four control registers; A, B, C, and D reside in both bank 0 and bank 1. These registers are accessible
at all times, even during the update cycle.
NONVOLATILE RAM—RTC
The 114 general-purpose nonvolatile RAM bytes are not dedicated to any special function within the
DS1689/DS1693. They can be used by the application program as nonvolatile memory and are fully
available during the update cycle. This memory is directly accessible when bank 0 is selected.
INTERRUPT CONTROL
The DS1689/DS1693 include six separate, fully automatic sources of interrupt for a processor:
1. Alarm interrupt
2. Periodic interrupt
3. Update-ended interrupt
4. Wake-up interrupt
5. Kickstart interrupt
6. RAM clear interrupt
The conditions, which generate each of these independent interrupt conditions, are described in greater
detail elsewhere in this data sheet. This section describes the overall control of the interrupts.
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