参数资料
型号: DS1862AB+
厂商: Maxim Integrated
文件页数: 20/42页
文件大小: 0K
描述: IC LASR CTRLR 7CHAN 5.5V 25CSBGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 126
类型: 激光二极管控制器(光纤)
数据速率: 10Gbps
通道数: 7
电源电压: 2.9 V ~ 5.5 V
电流 - 电源: 3mA
工作温度: -40°C ~ 100°C
封装/外壳: 25-TFBGA,CSPBGA
供应商设备封装: 25-BGA(5x5)
包装: 管件
安装类型: 表面贴装
XFP Laser Control and Digital Diagnostic IC
/* Assume that the Null input is 0.5V. */
/* In addition, the requirement for LSB is 50μV. */
FS = 65536 * 50e-6; /* 3.2768 */
CNT1 = 0.5 / 50e-6; /* 10000 */
CNT2 = 0.90*FS / 50e-6; /* 58982 */
/* Thus the NULL input of 0.5V and the 90% of FS input
is 2.94912V. */
set the trim-offset-register to zero;
set Right-Shift register to zero (Typically zero.
See the Right-Shifting section);
gain_result = 0h;
CLAMP = FFF8h/2^(Right_Shift_Register);
For n = 15 down to 0
begin
gain_result = gain_result + 2^n;
Force the 90% FS input (2.94912V);
Meas2 = read the digital result from the part;
If Meas2 >= CLAMP then
gain_result = gain_result - 2^n;
Right-Shifting A/D Conversion Result
(Scalable Dynamic Ranging)
Right-shifting is a digital method used to regain some
of the lost ADC range of a calibrated system. If right-
shifting is enabled, by simply loading a non-zero value
into the appropriate Right-Shifting Register, then the
DS1862A shifts the calibrated result just before it is
stored into the monitor channels’ register. If a system is
calibrated so the maximum expected input results in a
digital output value of less than 7FFFh (50% of FS),
then it is a candidate for using the right-shifting
method.
If the maximum desired digital output is less than
7FFFh, then the calibrated system is using less than 1/2
the ADC’s range. Similarly, if the maximum desired dig-
ital output is less than 1FFFh, then the calibrated sys-
tem is only using 1/8th the ADC’s range. For example, if
an applied maximum analog signal yields a maximum
digital output less than 1FFCh, then only 1/8th of the
ADC’s range is used. Right-shifting improves the reso-
lution of the measured signal as part of internal calibra-
tion. Without right-shifting, the 3 MS bits of the ADC will
never be used. In this example, a value of 3 for the
right-shifting maximizes the ADC range and a larger
Else
end;
Force the NULL input (0.5V);
Meas1 = read the digital result from the part;
if (Meas2 - Meas1) > (CNT2 - CNT1) then
gain_result = gain_result - 2^n;
gain setting must be loaded to achieve optimal conver-
sion. No resolution is lost since this is a 13-bit converter
that is left justified. The value can be right-shifted 3
times without losing any resolution. The following table
describes when the right-shifting method can be effec-
tively used.
Set the gain register to gain_result;
Table 10. Right-Shifting Selection
OFFSET _ REGISTER = ?
?
?
?
The  gain  register  is  now  set  and  the  resolution  of  the
conversion will best match the expected LSB. The next
step is to calibrate the offset of the DS1862A. With the
correct gain value written to the gain register, again
force the NULL input to the monitor pin. Read the digi-
tal result from the part (Meas1). The offset value is
equal to negative value of Meas1.
? ( ? 1)Meas1 ?
4
The calculated offset is now written to the DS1862A
and the gain and offset-scaling procedure is complete.
OUTPUT RANGE USED WITH
ZERO RIGHT-SHIFTS
0h .. FFFFh
0h .. 7FFFh
0h .. 3FFFh
0h .. 1FFFh
0h .. 0FFFh
NUMBER OF RIGHT-
SHIFTS NEEDED
0
1
2
3
4
20
______________________________________________________________________________________
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