参数资料
| 型号： | DS1874T+ |
| 厂商： | Maxim Integrated |
| 文件页数： | 18/88页 |
| 文件大小： | 0K |
| 描述： | IC CTLR SFP+ ANLG LDD 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 60 |
| 类型： | 激光二极管控制器 |
| 通道数： | 1 |
| 电源电压： | 2.85 V ~ 3.9 V |
| 电流 - 电源： | 2.5mA |
| 工作温度： | -40°C ~ 95°C |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（5x5） |
| 包装： | 管件 |
| 安装类型： | 表面贴装 |
| 其它名称： | 90-1874T+000 |
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SFP+ Controller with Digital LDD Interface
Table 4. MON3 Hysteresis Threshold
MON3
TIMESLICE
Values
NUMBER OF
RIGHT-SHIFTS
FINE MODE
MAX (hex)
COARSE MODE
MIN* (hex)
PERFORM FINE-
MODE CONVERSION
DID PRIOR MON3
0
1
2
3
4
FFF8
7FFC
3FFE
1FFF
0FFF
F000
7800
3C00
1E00
0F00
TIMESLICE RESULT IN A
COARSE CONVERSION?
(LAST RSSIR = 1?)
Y
5
6
7
07FF
03FF
01FF
0780
03C0
01E0
N
N
WAS CURRENT FINE-
*This is the minimum reported coarse-mode conversion.
MODE CONVERSION
≥ 93.75% OF FS?
Table 5. MON3 Configuration Registers
DID CURRENT FINE-
MODE CONVERSION
REACH MAX?
Y
Y
PERFORM COARSE-
REGISTER
GAIN
FINE MODE
98h –99h, Table 02h
COARSE MODE
9Ch –9Dh, Table 02h
MODE CONVERSION
OFFSET
A8h –A9h, Table 02h ACh –ADh, Table 02h
N
RIGHT-SHIFT 0
8Fh, Table 02h
—
LAST RSSI = 0
REPORT FINE
CONVERSION RESULT
LAST RSSIR = 1
REPORT COARSE
CONVERSION RESULT
CNFGC
UPDATE
(RSSIR BIT)
MON3 VALUE
8Bh, Table 02h
6Fh, Lower Memory
68h –69h, Lower Memory
implemented. The fine-mode conversion is compared to
one of two thresholds. The actual threshold values are a
function of the number of right-shifts being used. With
the use of right-shifting, the fine mode full-scale is pro-
END OF MON3
TIMESLICE
Figure 7. RSSI Flowchart
Then, depending on whether the last MON3 timeslice
resulted in a coarse-mode conversion and also depend-
ing on the value of the current fine conversion, decisions
are made whether to use the current fine-mode conver-
sion result or to make an additional conversion (within
the same MON3 timeslice), using coarse mode (using
coarse mode’s gain and offset settings and no right-
shifting) and reporting the coarse-mode result. The flow-
chart in Figure 7 also illustrates how hysteresis is
grammed to (1/2 n th) of the coarse mode full-scale. The
DS1874 now auto ranges to choose the range that gives
the best resolution for the measurement. Hysteresis is
applied to eliminate chatter when the input resides at
the boundary of the two ranges. See Figure 7 for details.
Table 4 shows the threshold values for each possible
number of right-shifts.
The RSSI_FF and RSSI_FC bits are used to force fine-
mode or coarse-mode conversions, or to disable the
dual-range functionality. Dual-range functionality is
enabled by default (both RSSI_FC and RSSI_FF are
factory programmed to 0 in EEPROM). It can be dis-
abled by setting RSSI_FC to 0 and RSSI_FF to 1. These
bits are also useful when calibrating MON3. For addi-
tional information, see Figure 19.
18
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| DS1874T+ | 功能描述:ADC / DAC多通道 SFP+ Controller w/ Dgtl LDD Interface RoHS:否 制造商:Texas Instruments 转换速率: 分辨率:8 bit 接口类型:SPI 电压参考: 电源电压-最大:3.6 V 电源电压-最小:2 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-40 |
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