参数资料
型号: DS1874T+
厂商: Maxim Integrated
文件页数: 8/88页
文件大小: 0K
描述: IC CTLR SFP+ ANLG LDD 28-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 60
类型: 激光二极管控制器
通道数: 1
电源电压: 2.85 V ~ 3.9 V
电流 - 电源: 2.5mA
工作温度: -40°C ~ 95°C
封装/外壳: 28-WFQFN 裸露焊盘
供应商设备封装: 28-TQFN-EP(5x5)
包装: 管件
安装类型: 表面贴装
其它名称: 90-1874T+000

SFP+ Controller with Digital LDD Interface
I 2 C AC ELECTRICAL CHARACTERISTICS
(V CC = +2.85V to +3.9V, T A = -40°C to +95°C, timing referenced to V IL(MAX) and V IH(MIN) , unless otherwise noted. See Figure 17.)
PARAMETER
SCL Clock Frequency
SYMBOL
f SCL
(Note 13)
CONDITIONS
MIN
0
TYP
MAX
400
UNITS
kHz
Clock Pulse-Width Low
Clock Pulse-Width High
Bus-Free Time Between STOP and START
Condition
START Hold Time
START Setup Time
t LOW
t HIGH
t BUF
t HD:STA
t SU:STA
1.3
0.6
1.3
0.6
0.6
μs
μs
μs
μs
μs
Data Out Hold Time
Data In Setup Time
t HD:DAT
t SU:DAT
0
100
0.9
μs
ns
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
STOP Setup Time
EEPROM Write Time
Capacitive Load for Each Bus Line
t R
t F
t SU:STO
t W
C B
(Note 14)
(Note 14)
(Note 15)
20 + 0.1C B
20 + 0.1C B
0.6
300
300
20
400
ns
ns
μs
ms
pF
NONVOLATILE MEMORY CHARACTERISTICS
(V CC = +2.85V to +3.9V, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EEPROM Write Cycles
At +25°C
At +85°C
200,000
50,000
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
All voltages are referenced to ground. Current into the IC is positive, and current out of the IC is negative.
Inputs are at supply rail. Outputs are not loaded.
This parameter is guaranteed by design.
Full-scale is user programmable.
The DACs are the bias and modulation DACs found in the MAX3798/MAX3799 that are controlled by the DS1874.
The DS1874 is configured with TXDOUT connected to the MAX3798/MAX3799 DISABLE input.
This includes writing to the modulation DAC and the initial step written to the bias DAC.
A temperature conversion is completed and the modulation register value is recalled from the LUT and V CC has been
measured to be above V CC LO alarm.
The timing is determined by the choice of the update rate setting (see Table 02h, Register 88h).
This specification is the time it takes from MON3 voltage falling below the LLOS trip threshold to LOSOUT asserted high.
This specification is the time it takes from MON3 voltage rising above the HLOS trip threshold to LOSOUT asserted low.
Assuming an appropriate initial step is programmed that would cause the power to exceed the APC set point within four
steps, the bias current will be within 3% within the time specified by the binary search time. See the BIAS and MODULA-
TION Control During Power-Up section.
I 2 C interface timing shown is for fast mode (400kHz). This device is also backward compatible with I 2 C standard mode
timing.
C B —the total capacitance of one bus line in pF.
EEPROM write begins after a STOP condition occurs.
8
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