参数资料
型号: DS21352L
厂商: Maxim Integrated Products
文件页数: 104/137页
文件大小: 0K
描述: IC TXRX T1 1-CHIP 3.3V 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
产品变化通告: Product Discontinuation 20/Feb/2012
标准包装: 90
功能: 单芯片收发器
接口: HDLC,T1
电路数: 1
电源电压: 3.14 V ~ 3.47 V
电流 - 电源: 75mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 托盘
包括: DSX-1 和 CSU 线路补偿发生器,HDLC 控制器,带内回路代码发生器和检测器
DS21352/DS21552
69 of 137
Like the SR1 and SR2 status registers, the HSR register has the unique ability to initiate a hardware
interrupt via the INT* output pin. Each of the events in the HSR can be either masked or unmasked from
the interrupt pin via the HDLC Interrupt Mask Register (HIMR). Interrupts will force the INT* pin low
when the event occurs. The INT pin will be allowed to return high (if no other interrupts are present)
when the user reads the event bit that caused the interrupt to occur.
15.3.3 BASIC OPERATION DETAILS
To allow the framer to properly source/receive data from/to the HDLC and BOC controller the legacy FDL circuitry (which is
described in Section 15.4) should be disabled and the following bits should be programmed as shown:
TCR1.2 = 1 (source FDL data from the HDLC and BOC controller)
TBOC.6 = 1 (enable HDLC and BOC controller)
CCR2.5 = 0 (disable SLC–96 and D4 Fs–bit insertion)
CCR2.4 = 0 (disable legacy FDL zero stuffer)
CCR2.1 = 0 (disable SLC–96 reception)
CCR2.0 = 0 (disable legacy FDL zero stuffer)
IMR2.4 = 0 (disable legacy receive FDL buffer full interrupt)
IMR2.3 = 0 (disable legacy transmit FDL buffer empty interrupt)
IMR2.2 = 0 (disable legacy FDL match interrupt)
IMR2.1 = 0 (disable legacy FDL abort interrupt).
As a basic guideline for interpreting and sending both HDLC messages and BOC messages, the following sequences can be
applied:
15.3.3.1 RECEIVE AN HDLC MESSAGE OR A BOC
1) Enable RBOC and RPS interrupts.
2) Wait for interrupt to occur.
3) If RBOC=1, then follow steps 5 and 6.
4) If RPS=1, then follow steps 7 through 13.
5) If LBD=1, a BOC is present, then read the code from the RBOC register and take action as needed.
6) If BD=0, a BOC has ceased, take action as needed and then return to step 1.
7) Disable RPS interrupt and enable either RPE, RNE, or RHALF interrupt.
8) Read RHIR to obtain REMPTY status.
a) If REMPTY=0, then record OBYTE, CBYTE, and POK bits and then read the FIFO.
i)
If CBYTE=0 then skip to step 9.
ii) If CBYTE=1 then skip to step 11.
b) If REMPTY=1, then skip to step 10.
9) Repeat step 8.
10) Wait for interrupt, skip to step 8.
11) If POK=0, then discard whole packet.
12) If POK=1, accept the packet.
13) Disable RPE, RNE, or RHALF interrupt, enable RPS interrupt and return to step 1.
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