参数资料
型号: DS21352L
厂商: Maxim Integrated Products
文件页数: 12/137页
文件大小: 0K
描述: IC TXRX T1 1-CHIP 3.3V 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
产品变化通告: Product Discontinuation 20/Feb/2012
标准包装: 90
功能: 单芯片收发器
接口: HDLC,T1
电路数: 1
电源电压: 3.14 V ~ 3.47 V
电流 - 电源: 75mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 托盘
包括: DSX-1 和 CSU 线路补偿发生器,HDLC 控制器,带内回路代码发生器和检测器
DS21352/DS21552
109 of 137
20.1 CHANNEL INTERLEAVE
In channel interleave mode data is output to the PCM Data Out bus one channel at a time from each of the
connected SCTs until all channels of frame n from all each SCT has been place on the bus. This mode
can be used even when the connected SCTs are operating asynchronous to each other. The elastic stores
will manage slip conditions. See Figure 21-13 for details.
20.2 FRAME INTERLEAVE
In frame interleave mode data is output to the PCM Data Out bus one frame at a time from each of the
connected SCTs. This mode is used only when all connected SCTs are synchronous. In this mode, slip
conditions are not allowed. See Figure 21-14 for details.
21. FUNCTIONAL TIMING DIAGRAMS
Figure 21-1 RECEIVE SIDE D4 TIMING
Notes:
1. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is not enabled (RCR2.5 = 0)
2. RSYNC in the frame mode (RCR2.4 = 0) and double-wide frame sync is enabled (RCR2.5 = 1)
3. RSYNC in the multiframe mode (RCR2.4 = 1)
4. RLINK data (Fs - bits) is updated one bit prior to even frames and held for two frames
5. RLINK and RLCLK are not synchronous with RSYNC when the receive side elastic store is enabled
FRAME#
1
2
345
678
9
10
11
12
1
2
3
45
4
RLINK
RLCLK
3
RSYNC
1
RSYNC
RFSYNC
2
RSYNC
相关PDF资料
PDF描述
VI-B5K-IY-F1 CONVERTER MOD DC/DC 40V 50W
DS21554L IC TXRX E1 1-CHIP 5V 100-LQFP
VI-B5J-IY-F2 CONVERTER MOD DC/DC 36V 50W
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