参数资料
型号: DS21352L
厂商: Maxim Integrated Products
文件页数: 90/137页
文件大小: 0K
描述: IC TXRX T1 1-CHIP 3.3V 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
产品变化通告: Product Discontinuation 20/Feb/2012
标准包装: 90
功能: 单芯片收发器
接口: HDLC,T1
电路数: 1
电源电压: 3.14 V ~ 3.47 V
电流 - 电源: 75mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 托盘
包括: DSX-1 和 CSU 线路补偿发生器,HDLC 控制器,带内回路代码发生器和检测器
DS21352/DS21552
56 of 137
B5
RDS0M.3
Receive DS0 Channel Bit 5.
B6
RDS0M.2
Receive DS0 Channel Bit 6.
B7
RDS0M.1
Receive DS0 Channel Bit 7.
B8
RDS0M.0
Receive DS0 Channel Bit 8. LSB of the DS0 channel (last bit to be received).
10. SIGNALING OPERATION
Processor based (i.e., software based) signaling access and hardware based access are available.
Processor based access and hardware based access can be used simultaneously if necessary. The
processor based signaling is covered in Section 10-1 and the hardware based signaling is covered in
Section 10-2.
10.1 PROCESSOR BASED SIGNALING
The robbed–bit signaling bits embedded in the T1 stream can be extracted from the receive stream and
inserted into the transmit stream by each framer. There is a set of 12 registers for the receive side (RS1 to
RS12) and 12 registers on the transmit side (TS1 to TS12). The signaling registers are detailed below.
The CCR1.5 bit is used to control the robbed signaling bits as they appear at RSER. If CCR1.5 is set to
zero, then the robbed signaling bits will appear at the RSER pin in their proper position as they are
received. If CCR1.5 is set to a one, then the robbed signaling bit positions will be forced to a one at
RSER. If hardware based signaling is being used, then CCR1.5 must be set to zero.
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