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参数资料
| 型号： | DS2172T/T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 19/22页 |
| 文件大小： | 0K |
| 描述： | IC TESTER BIT ERROR RATE 32-TQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS |
| 产品变化通告： | Product Discontinuation 20/Feb/2012 |
| 标准包装： | 250 |
| 功能： | 位误码率测试器（BERT） |
| 接口： | T1 |
| 电路数： | 1 |
| 电源电压： | 4.5 V ~ 5.5 V |
| 电流 - 电源： | 10mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-TQFP |
| 供应商设备封装： | 32-TQFP（7x7） |
| 包装： | 带卷 (TR) |
| 包括： | 错误计数器，样式发生器和检测器 |
DS2172
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2.0 PARALLEL CONTROL INTERFACE
The DS2172 is controlled via a multiplexed bi-directional address/data bus by an external microcontroller
or microprocessor. The DS2172 can operate with either Intel or Motorola bus timing configurations. If
the BTS pin is tied low, Intel timing will be selected; if tied high, Motorola timing will be selected. All
Motorola bus signals are listed in parenthesis (). See the timing diagrams in the A.C. Electrical
Characteristics for more details. The multiplexed bus on the DS2172 saves pins because the address
information and data information share the same signal paths. The addresses are presented to the pins in
the first portion of the bus cycle and data will be transferred on the pins during second portion of the bus
cycle. Addresses must be valid prior to the falling edge of ALE(AS), at which time the DS2172 latches
the address from the AD0 to AD7 pins. Valid write data must be present and held stable during the later
portion of the DS or WR pulses. In a read cycle, the DS2172 outputs a byte of data during the latter
portion of the DS or RD pulses. The read cycle is terminated and the bus returns to a high impedance
state as RD transitions high in Intel timing or as DS transitions low in Motorola timing. The DS2172 can
also be easily connected to non-multiplexed buses. RCLK and TCLK are used to update counters and
load transmit and receive pattern registers. At slow clock rates, sufficient time must be allowed for these
port operations.
3.0 PATTERN SET REGISTERS
The Pattern Set Registers (PSR) are loaded each time a new pattern (whether it be pseudorandom or
repetitive) is to be generated. When a pseudorandom pattern is generated, all four PSRs must be loaded
with FF Hex. When a repetitive pattern is to be created, the four PSRs are loaded with the pattern that is
to be repeated. Please see Tables 4 and 5 for some programming examples.
PATTERN SET REGISTERS
(MSB)
(LSB)
PS31
PS30
PS29
PS28
PS27
PS26
PS25
PS24
PSR3 (addr.=00 Hex)
PS23
PS22
PS21
PS20
PS19
PS18
PS17
PS16
PSR2 (addr.=01 Hex)
PS15
PS14
PS13
PS12
PS11
PS10
PS9
PS8
PSR1 (addr.=02 Hex)
PS7
PS6
PS5
PS4
PS3
PS2
PS1
PS0
PSR0 (addr.=03 Hex)
4.0 PATTERN LENGTH REGISTER
Length Bits LB4 to LB0 determine the length of the pseudorandom polynomial or programmable
repetitive pattern that is generated and detected. With the pseudorandom patterns, the “Tap A” feedback
position of the pattern generator is always equal to the value in the Pattern Length Register (PLR). Please
refer to Figure 2 for a block diagram of the pattern generator and to Tables 4 and 5 for some
programming examples.
PLR: PATTERN LENGTH REGISTER (Address=04 Hex)
(MSB)
(LSB)
-
LB4
LB3
LB2
LB1
LB0
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相关代理商/技术参数 |
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| DS2174 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:EBERT |
| DS2174DK | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Enhanced Bit Error-Rate Tester Design Kit |
| DS2174Q | 功能描述:电信集成电路 Enhanced Bit Error Rate Tester (BERT) RoHS:否 制造商:STMicroelectronics 类型:Telecom IC - Various 工作电源电压:4.75 V to 5.25 V 电源电流: 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-100 封装:Tray |
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| DS2174Q/T&R | 功能描述:电信集成电路 RoHS:否 制造商:STMicroelectronics 类型:Telecom IC - Various 工作电源电压:4.75 V to 5.25 V 电源电流: 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:PQFP-100 封装:Tray |
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