参数资料
| 型号： | DS2430A+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 12/19页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 256BIT TO92-3 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 256（32 x 8） |
| 接口： | 1 线 串行 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | TO-226-3、TO-92-3（TO-226AA）成形引线 |
| 供应商设备封装： | TO-92-3 |
| 包装： | 带卷 (TR) |
DS2430A
After one complete pass, the bus master knows the contents of the ROM in one device. The remaining
number of devices and their ROM codes may be identified by additional passes. See Application Note
187 for a comprehensive discussion of a search ROM, including an actual example.
1-Wire Signaling
The DS2430A requires strict protocols to insure data integrity. The protocol consists of four types of
signaling on one line: Reset Sequence with Reset Pulse and Presence Pulse, Write-0, Write-1 and Read-
Data. All these signals (except Presence Pulse) are initiated by the bus master.
To get from idle to active, the voltage on the 1-Wire line needs to fall from V PUP below the threshold V TL .
To get from active to idle, the voltage needs to rise from V ILMAX past the threshold V TH . The time it takes
for the voltage to make this rise is seen in Figure 9 as ε , and its duration depends on the pullup resistor
(R PUP ) used and the capacitance of the 1-Wire network attached. The voltage V ILMAX is relevant for the
DS2430A when determining a logical level, not triggering any events.
Figure 9 shows the initialization sequence required to begin any communication with the DS2430A. A
Reset Pulse followed by a Presence Pulse indicates the DS2430A is ready to receive data, given the
correct ROM and memory function command. If the bus master uses slew-rate control on the falling
edge, it must pull down the line for t RSTL + t F to compensate for the edge.
After the bus master has released the line it goes into Receive mode. Now the 1-Wire bus is pulled to
V PUP through the pullup resistor. When the threshold V TH is crossed, the DS2340A waits for t PDH and then
transmits a Presence Pulse by pulling the line low for t PDL . To detect a Presence Pulse, the master must
test the logical state of the 1-Wire line at t MSP . The t RSTH window must be at least the sum of t PDHMAX ,
t PDLMAX , and t RECMIN . Immediately after t RSTH is expired, the DS2430A is ready for data communication.
INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 9
MASTER TX “RESET PULSE” MASTER RX “PRESENCE PULSE”
V PUP
V IHMASTER
V TH
V TL
V ILMAX
ε
t MSP
0V
t F
t RSTL
t PDH
t PDL
t RSTH
t REC
RESISTOR
MASTER
DS2430A
Read/Write Time Slots
Data communication with the DS2430A takes place in time slots, which carry a single bit each. Write
time slots transport data from bus master to slave. Read time slots transfer data from slave to master.
Figure 10 illustrates the definitions of the write and read time slots.
All communication begins with the master pulling the data line low. As the voltage on the 1-Wire line
falls below the threshold V TL , the DS2430A starts its internal timing generator that determines when the
data line is sampled during a write time slot and how long data is valid during a read time slot.
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相关代理商/技术参数 |
参数描述 |
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| DS2430AV | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:256-Bit 1-Wire EEPROM |
| DS2430AX | 功能描述:电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| DS2430AX#T&R | 功能描述:电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| DS2430AX#U | 功能描述:电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| DS2430AX-S | 功能描述:电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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