参数资料
| 型号： | DS2430A+T&R |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 17/19页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 256BIT TO92-3 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 256（32 x 8） |
| 接口： | 1 线 串行 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | TO-226-3、TO-92-3（TO-226AA）成形引线 |
| 供应商设备封装： | TO-92-3 |
| 包装： | 带卷 (TR) |
ELECTRICAL CHARACTERISTICS (continued)
(T A = -40 ° C to +85 ° C, unless otherwise noted.) (Note 1)
DS2430A
Note 1:
Note 2:
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Note 24:
Limits are 100% production tested at T A = +25°C and/or T A = +85°C. Limits over the operating temperature
range and relevant supply voltage range are guaranteed by design and characterization. Typical values are not
guaranteed.
System requirement.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire
recovery times. The specified value here applies to systems with only one device and with the minimum t REC . For
more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may
be required. If longer t REC is used, higher R PUP values may be able to be tolerated.
Maximum value represents the internal parasite capacitance when V PUP is first applied. If a 2.2k ? resistor is used
to pull up the data line, 2.5μs after V PUP has been applied the parasite capacitance will not affect normal
communications.
Guaranteed by design, characterization and/or simulation only. Not production tested.
V TL , V TH , and V HY are a function of the internal supply voltage which is itself a function of V PUP , R PUP , 1-Wire
timing, and capacitive loading on DATA. Lower V PUP , higher R PUP , shorter t REC , and heavier capacitive loading
all lead to lower values of V TL , V TH , and V HY .
Voltage below which, during a falling edge on DATA, a logic 0 is detected.
The voltage on DATA needs to be less or equal to V IL(MAX) at all times the master is driving DATA to a logic-0
level.
Voltage above which, during a rising edge on DATA, a logic 1 is detected.
After V TH is crossed during a rising edge on DATA, the voltage on DATA has to drop by at least V HY to be
detected as logic '0'.
The I-V characteristic is linear for voltages less than 1V.
Applies to a single device attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at t REH after V TH has been reached on the preceding rising
edge.
Defines maximum possible bit rate. Equal to 1/(t W0L(min) + t REC(min) ).
Interval after t RSTL during which a bus master is guaranteed to sample a logic-0 on DATA if there is a DS2430A
present. Minimum limit is t PDH(max) ; maximum limit is t PDH(min) + t PDL(min) .
ε in Figure 10 represents the time required for the pullup circuitry to pull the voltage on DATA up from V IL to
V TH . The actual maximum duration for the master to pull the line low is t W1Lmax + t F and t W0Lmax + t F respectively.
δ in Figure 10 represents the time required for the pullup circuitry to pull the voltage on DATA up from V IL to the
input high threshold of the bus master. The actual maximum duration for the master to pull the line low is
t RLmax + t F .
Current drawn from DATA during the EEPROM programming interval. The pullup circuit on DATA during the
programming interval should be such that the voltage at DATA is greater than or equal to V PUPMIN . If V PUP in the
system is close to V PUPMIN , a low-impedance bypass of R PUP , which can be activated during programming, may
need to be added.
Interval begins t REHmax after the trailing rising edge on DATA for the last timeslot of the validation key for a valid
copy sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the
current drawn by the device has returned from I PROG to I L .
Write-cycle endurance is degraded as T A increases.
Not 100% production-tested; guaranteed by reliability monitor sampling.
Data retention is degraded as T A increases.
Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production
test to data sheet limit at operating temperature range is established by reliability testing.
EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at
elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40
years at +85°C.
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相关代理商/技术参数 |
参数描述 |
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| DS2430AV | 制造商:DALLAS 制造商全称:Dallas Semiconductor 功能描述:256-Bit 1-Wire EEPROM |
| DS2430AX | 功能描述:电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| DS2430AX#T&R | 功能描述:电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| DS2430AX#U | 功能描述:电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
| DS2430AX-S | 功能描述:电可擦除可编程只读存储器 RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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