DS26334 3.3V, 16-Channel, E1/T1/J1 Short/Long-Haul Line Interface Unit
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5.4.7 Transmit All Ones
When Transmit All Ones is invoked continuous Ones are transmitted using MCLK as the Timing Reference. Data
input at TPOS and TNEG is ignored.
Transmit All ones can be sent by setting bits in the
TAOE
Register. Also Transmit All ones will be enabled if bits in
Register
ATAOS
are set and the corresponding receiver goes into LOS state in status register
LOSS.
5.4.8 Drive Failure Monitor
The Driver Fail Monitor is connected to the TTIP and TRING pins. It will detect a Short or Open Circuit on the
Secondary side of the Transmit Transformer. The drive current will be limited to 50 ma if a short circuit is detected.
The
DFMS
status registers and the corresponding Interrupt and Enable Registers can be used to monitor the driver
failure.
5.5 Receiver
The 16 receivers of DS26334 are all identical. Either a 2:1 or 1:1 transformer can be used on the receive side
(selected by the RTR bit). The DS26334 is designed to be fully software-selectable for E1 and T1/J1 without the
need to change any external resistors for the receive-side. The receive impedance match settings are controlled by
the transmit template/impedance selection. See
Figure 5-8
and
Table 5-6
for external component values. All
internal impedance matching is enabled via the RIMPON bit.
The peak detector and data slicer process the received signal. The output of the data slicer goes to clock and data
recovery. A 2.048/1.544 PLL is internally multiplied by 16 via another internal PLL and fed to the clock recovery
system derives E1 or T1 clock. The clock recovery system uses the clock from the PLL circuit to form an 16 times
over sampler, which is used to recover the clock and data. This over sampling technique offers outstanding
performance to meet jitter tolerance specifications. Dependent on selection options B8ZS/HDB3/AMI decoding is
performed. These decoded data is provided to the system side in either single-rail or dual-rail mode. The selection
of single rail or dual rail is done by settings in the
SRMS
register.
The receiver is capable of recovering signals up to 36dB worth of attenuation for T1 mode, and up to 43dB for E1
mode. The receiver contains functionality to provide resistive gain up to 32 dB for monitor mode.
5.5.1 Receiver Monitor Mode
The receive equalizer is equipped with monitor mode function that allows for resistive gain up to 32dB, along with
cable attenuation of 6dB to 24dB as shown in the
RSMM1–4
register.
5.5.2 Peak Detector and Slicer
The Slicer determines the polarity and presence of the received data. The output of the Slicer is sent to the Clock
and Data Recovery circuitry for extraction of data and clock. The slicer has a built-in peak detector for
determination of the slicing threshold.
5.5.3 Receive Level Indicator
The DS26334 will report the signal strength at RTIP and RRING in increments described in
Table 6-18.
via register
bits CnRL3-C
n
RL0 located in the
RSL1–4
register.