DS26503 T1/E1/J1 BITS Element
2 of 123
TABLE OF CONTENTS
1.
FEATURES.......................................................................................................................7
1.1
1.2
1.3
1.4
1.5
1.6
G
ENERAL
........................................................................................................................7
L
INE
I
NTERFACE
...............................................................................................................7
J
ITTER
A
TTENUATOR
........................................................................................................7
F
RAMER
/F
ORMATTER
.......................................................................................................8
T
EST AND
D
IAGNOSTICS
...................................................................................................8
C
ONTROL
P
ORT
...............................................................................................................8
2.
SPECIFICATIONS COMPLIANCE...................................................................................9
3.
BLOCK DIAGRAMS.......................................................................................................12
4.
PIN FUNCTION DESCRIPTION .....................................................................................15
4.1
4.2
4.3
4.4
4.5
4.6
4.7
T
RANSMIT
PLL...............................................................................................................15
T
RANSMIT
S
IDE
..............................................................................................................15
R
ECEIVE
S
IDE
................................................................................................................16
C
ONTROLLER
I
NTERFACE
................................................................................................17
JTAG ...........................................................................................................................21
L
INE
I
NTERFACE
.............................................................................................................21
P
OWER
.........................................................................................................................22
5.
PINOUT...........................................................................................................................23
6.
HARDWARE CONTROLLER INTERFACE....................................................................26
6.1
6.2
6.3
6.4
6.5
6.6
6.7
T
RANSMIT
C
LOCK
S
OURCE
.............................................................................................26
I
NTERNAL
T
ERMINATION
..................................................................................................26
L
INE
B
UILD
-O
UT
.............................................................................................................27
R
ECEIVER
O
PERATING
M
ODES
........................................................................................27
T
RANSMITTER
O
PERATING
M
ODES
..................................................................................28
MCLK P
RE
-S
CALER
......................................................................................................28
O
THER
H
ARDWARE
C
ONTROLLER
M
ODE
F
EATURES
.........................................................29
7.
PROCESSOR INTERFACE............................................................................................30
7.1
7.2
P
ARALLEL
P
ORT
F
UNCTIONAL
D
ESCRIPTION
.....................................................................30
SPI S
ERIAL
P
ORT
I
NTERFACE
F
UNCTIONAL
D
ESCRIPTION
.................................................30
Clock Phase and Polarity ................................................................................................... 30
Bit Order............................................................................................................................. 30
Control Byte ....................................................................................................................... 30
Burst Mode......................................................................................................................... 30
Register Writes................................................................................................................... 31
Register Reads .................................................................................................................. 31
R
EGISTER
M
AP
..............................................................................................................32
Power-Up Sequence.......................................................................................................... 34
Test Reset Register............................................................................................................ 34
Mode Configuration Register.............................................................................................. 35
I
NTERRUPT
H
ANDLING
....................................................................................................38
S
TATUS
R
EGISTERS
.......................................................................................................38
I
NFORMATION
R
EGISTERS
...............................................................................................39
I
NTERRUPT
I
NFORMATION
R
EGISTERS
..............................................................................39
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7.3
7.3.1
7.3.2
7.3.3
7.4
7.5
7.6
7.7