参数资料
型号: DS26503
厂商: Maxim Integrated Products, Inc.
英文描述: T1/E1/J1/64KCC BITS Element
中文描述: T1/E1/J1 BITS单元
文件页数: 52/123页
文件大小: 995K
代理商: DS26503
DS26503 T1/E1/J1 BITS Element
52 of 123
10. I/O PIN CONFIGURATION OPTIONS
Register Name:
IOCR1
Register Description:
I/O Configuration Register 1
Register Address:
01h
Bit #
7
6
Name
RSMS2
Default
0
0
HW
Mode
Bit 0/Output Data Format (ODF).
0 = bipolar data at TPOS and TNEG
1 = NRZ data at TPOS; TNEG = 0
Bit 1/TS I/O Select (TSIO).
This bit determines whether the TS pin is an input or and output. See
Table 10-1
.
0 = TS is an input
1 = TS is an output
Bit 2/TS Mode Select (TSM).
In T1 or E1 operation, selects frame or multiframe mode for the TS pin. In 6312kHz mode, this
bit should be set = 0. See
Table 10-1
.
0 = frame mode
1 = multiframe mode
Bit 3/Transmit Signaling Double-Wide Sync (TSDW).
In T1 mode, setting this bit = 1 and setting TSIO = 1 will cause the
sync-pulse output on TS to be two clocks wide during signaling frames. In E1 or 6312kHz mode, this bit should be set = 0. See
Table 10-1
.
0 = (T1) normal sync pulses
1 = (T1) double-wide sync pulses during signaling frames
Bit 4/ RLOF Output Function (RLOFF).
In T1 or E1 receive mode this bit determines the function of the RLOF pin. In
6312kHz receive mode, this bit should be set = 0.
0 = receive loss of frame (RLOF)
1 = loss-of-transmit clock (LOTC)
Bit 5/RS Mode Select 1(RSMS1).
In T1 or E1 receive mode, this bit selects a frame or multiframe output pulse at RS pin.
IOCR.6 may be used to select other function for the RS pin.
0 = frame mode
1 = multiframe mode
Bit 6/RS Mode Select 2 (RSMS2).
In T1 and E1 receive mode, this bit along with IOCR.5 selects the function of the RS pin.
T1 Mode: (when IOCR.5 set = 0)
0 = do not pulse double-wide in signaling frames
1 = do pulse double-wide in signaling frames
E1 Mode: (when IOCR.5 set = 1)
0 = RS outputs CAS multiframe boundaries
1 = RS outputs CRC4 multiframe boundaries
Bit 7/Unused, must be set = 0 for proper operation
.
5
4
3
2
1
0
RSMS1
0
RSM
PIN 1
RLOFF
0
TSDW
0
TSM
0
TSM
PIN 2
TSIO
0
ODF
0
0
0
0
0
0
0
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