参数资料
型号: DS26503LN
英文描述: T1/E1/J1 BITS Element
中文描述: T1/E1/J1收发BITS的元素
文件页数: 49/123页
文件大小: 995K
代理商: DS26503LN
DS26503 T1/E1/J1 BITS Element
49 of 123
Table 9-2. E1 Alarm Criteria
ALARM
SET CRITERIA
CLEAR CRITERIA
ITU
SPEC.
RLOF
An
RLOF
condition exists on power-up
prior to initial synchronization, when a
resync criteria has been met, or when a
manual resync has been initiated via
E1RCR.0
255 or 2048 consecutive zeros received as
determined by E1RCR.0
Bit 3 of non-align frame set to one for
three consecutive occasions
RLOS
RRA
In 255-bit times, at least 32
ones are received
Bit 3 of non-align frame set to
zero for three consecutive
occasions
More than two zeros in two
frames (512 bits)
G.775/G.962
O.162
2.1.4
RUA1
Fewer than three zeros in two frames (512
bits)
Bit 6 of time slot 16 in frame 0 has been
set for two consecutive multiframes
Two out of three Sa7 bits are zero
O.162
1.6.1.2
RDMA
V52LNK
G.965
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
HW
Mode
Bits 0-3/Chip Revision Bits (ID0 to ID3).
The lower four bits of the IDR are used to display the die revision of the chip. IDO
is the LSB of a decimal code that represents the chip revision.
Bits 4-7/Device ID (ID4 to ID7).
The upper four bits of the IDR are used to display the DS26503 ID. The DS26503 ID is
0001.
IDR
Device Identification Register
10h
7
6
5
4
3
2
1
0
ID7
0
ID6
0
ID5
0
ID4
1
ID3
N
ID2
N
ID1
N
ID0
N
X
X
X
X
X
X
X
X
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