参数资料
型号: DS26503LN
英文描述: T1/E1/J1 BITS Element
中文描述: T1/E1/J1收发BITS的元素
文件页数: 98/123页
文件大小: 995K
代理商: DS26503LN
DS26503 T1/E1/J1 BITS Element
98 of 123
16. JTAG BOUNDARY SCAN ARCHITECTURE AND TEST ACCESS PORT
The DS26503 supports the standard IEEE 1149.1 instruction codes SAMPLE/PRELOAD, BYPASS, and
EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. The DS26503
contains the following as required by IEEE 1149.1 Standard Test Access Port and Boundary Scan
Architecture:
Test Access Port (TAP)
TAP Controller
Instruction Register
Bypass Register
Boundary Scan Register
Device Identification Register
Details on Boundary Scan Architecture and the Test Access Port can be found in IEEE 1149.1-1990,
IEEE 1149.1a-1993, and IEEE 1149.1b-1994.
The Test Access Port has the necessary interface pins:
JTRST
, JTCLK, JTMS, JTDI, and JTDO. See the
pin descriptions for details.
Figure 16-1. JTAG Functional Block Diagram
JTDI
JTMS
JTCLK
JTRST
JTDO
TEST ACCESS PORT
CONTROLLER
V
DD
V
DD
V
DD
BOUNDRY SCAN
REGISTER
BYPASS
REGISTER
INSTRUCTION
REGISTER
IDENTIFICATION
REGISTER
MUX
SELECT
OUTPUT ENABLE
10k
10k
10k
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