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参数资料
型号： DS26503LN
英文描述： T1/E1/J1 BITS Element
中文描述： T1/E1/J1收发BITS的元素
文件页数： 99/123页
文件大小： 995K
代理商： DS26503LN
DS26503 T1/E1/J1 BITS Element
99 of 123
TAP Controller State Machine
The TAP controller is a finite state machine that responds to the logic level at JTMS on the rising edge of
JTCLK. See
Figure 16-2
.
Test-Logic-Reset
Upon power-up, the TAP controller will be in the test-logic-reset state. The instruction register will
contain the IDCODE instruction. All system logic of the device will operate normally.
Run-Test-Idle
The run-test-idle is used between scan operations or during specific tests. The instruction register and test
registers will remain idle.
Select-DR-Scan
All test registers retain their previous state. With JTMS LOW, a rising edge of JTCLK moves the
controller into the capture-DR state and will initiate a scan sequence. JTMS HIGH during a rising edge
on JTCLK moves the controller to the select-IR-scan state.
Capture-DR
Data can be parallel-loaded into the test-data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the test
register will remain at its current value. On the rising edge of JTCLK, the controller will go to the shift-
DR state if JTMS is LOW or it will go to the exit1-DR state if JTMS is HIGH.
Shift-DR
The test-data register selected by the current instruction will be connected between JTDI and JTDO and
will shift data one stage toward its serial output on each rising edge of JTCLK. If a test register selected
by the current instruction is not placed in the serial path, it will maintain its previous state.
Exit1-DR
While in this state, a rising edge on JTCLK will put the controller in the update-DR state, which
terminates the scanning process, if JTMS is HIGH. A rising edge on JTCLK with JTMS LOW will put
the controller in the pause-DR state.
Pause-DR
Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction will retain their previous state. The controller will remain in this state while JTMS is LOW. A
rising edge on JTCLK with JTMS HIGH will put the controller in the exit2-DR state.
Exit2-DR
A rising edge on JTCLK with JTMS HIGH while in this state will put the controller in the update-DR
state and terminate the scanning process. A rising edge on JTCLK with JTMS LOW will enter the shift-
DR state.
Update-DR
A falling edge on JTCLK while in the update-DR state will latch the data from the shift register path of
the test registers into the data output latches. This prevents changes at the parallel output due to changes
in the shift register.
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相关代理商/技术参数
参数描述
DS26503LN+ 功能描述:计时器和支持产品 E1-T1-J1 Bits Element RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel
DS26504 制造商:Maxim Integrated Products 功能描述:T1/E1/J1 ENH BITS ELEMENT LQFP - Trays
DS26504_06 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:T1/E1/J1/64KCC BITS Element
DS26504DK 功能描述:网络开发工具 DS26504 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V
DS26504L 功能描述:计时器和支持产品 E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel
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