- 您现在的位置：买卖IC网 > PDF目录378591 > DS26503LN T1/E1/J1 BITS Element PDF资料下载
参数资料
| 型号： | DS26503LN |
| 英文描述： | T1/E1/J1 BITS Element |
| 中文描述： | T1/E1/J1收发BITS的元素 |
| 文件页数： | 80/123页 |
| 文件大小： | 995K |
| 代理商： | DS26503LN |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页当前第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页
DS26503 T1/E1/J1 BITS Element
80 of 123
The transmit line drive has two modes of operation: fixed gain or automatic gain. In the fixed gain mode,
the transmitter outputs a fixed current into the network load to achieve a nominal pulse amplitude. In the
automatic gain mode, the transmitter adjusts its output level to compensate for slight variances in the
network load. See the
Transmit Line Build-Out Control (TLBC)
register
for details.
13.3.1 Transmit Short-Circuit Detector/Limiter
The DS26503 has an automatic short-circuit limiter that limits the source current to 50mA (rms) into a
1 load. This feature can be disabled by setting the SCLD bit (LIC2.1) = 1. TCLE (SR1.2) provides a
real-time indication of when the current limiter is activated. If the current limiter is disabled, TCLE will
indicate that a short-circuit condition exist. Status Register SR1.2 provides a latched version of the
information, which can be used to activate an interrupt when enable via the IMR1 register. When set low,
the TPD bit (LIC1.0) will power-down the transmit line driver and tri-state the TTIP and TRING pins.
13.3.2 Transmit Open-Circuit Detector
The DS26503 can also detect when the TTIP or TRING outputs are open circuited. TOCD (SR1.1) will
provide a real-time indication of when an open circuit is detected. SR1 provides a latched version of the
information (SR1.1), which can be used to activate an interrupt when enable via the IMR1 register.
13.3.3 Transmit BPV Error Insertion
When IBPV (LIC2.5) is transitioned from a zero to a one, the device waits for the next occurrence of
three consecutive ones to insert a BPV. IBPV must be cleared and set again for another BPV error
insertion.
13.3.4 Transmit G.703 Section 10 Synchronization Signal (E1 Mode)
The DS26503 can transmit the 2.048MHz square-wave synchronization clock. To transmit the 2.048MHz
clock, when in E1 mode, set the mode configuration bits in the Mode Configuration Register (MCREG).
13.4 MCLK Pre-Scaler
A 16.384MHz, 8.192MHz, 4.096MHz, 2.048MHz, or 1.544MHz clock must be applied at MCLK. ITU
specification G.703 requires an accuracy of ±50ppm for both T1 and E1. TR62411 and ANSI specs require
an accuracy of ±32ppm for T1 interfaces. A prescaler will divide the 16MHz, 8MHz, or 4MHz clock down to
2.048MHz. There is a PLL for the jitter attenuator that will convert the 2.048MHz clock to a 1.544MHz rate
for T1 applications. Setting JACKS (LIC2.3) to a logic 0 bypasses this PLL.
13.5 Jitter Attenuator
The DS26503’s jitter attenuator can be set to a depth of either 32 bits or 128 bits via the JABDS bit
(LIC1.2). The 128-bit mode is used in applications where large excursions of wander are expected. The
32-bit mode is used in delay-sensitive applications. The characteristics of the attenuation are shown in
Figure 13-10
and
Figure 13-11
. The jitter attenuator can be placed in either the receive path or the
transmit path by appropriately setting or clearing the JAS bit (LIC1.3). If the part is configured for
hardware mode and the jitter attenuator is enabled, it will automatically be placed in the receive path. The
jitter attenuator can also be disabled (in effect, removed) by setting the DJA bit (LIC1.1). Either the
recovered clock from the clock/data recovery block or the clock applied at the TCLK pin is adjusted to
create a smooth jitter-free clock that is used to clock data out of the jitter attenuator FIFO. It is acceptable
to provide a gapped/bursty clock at the TCLK pin if the jitter attenuator is placed on the transmit side. If
the incoming jitter exceeds either 120 UI
P-P
(buffer depth is 128 bits) or 28 UI
P-P
(buffer depth is 32 bits),
then the DS26503 will divide the internal nominal 32.768MHz (E1) or 24.704MHz (T1) clock by either
相关PDF资料 |
PDF描述 |
|---|---|
| DS26503 | T1/E1/J1/64KCC BITS Element |
| DS26LV3 | 16 AMP LOW PROFILE POWER RELAY |
| DS2703 | SHA-1 Battery Pack Authentication IC |
| DS2703U | SHA-1 Battery Pack Authentication IC |
| DS2703UR | SHA-1 Battery Pack Authentication IC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DS26503LN+ | 功能描述:计时器和支持产品 E1-T1-J1 Bits Element RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
| DS26504 | 制造商:Maxim Integrated Products 功能描述:T1/E1/J1 ENH BITS ELEMENT LQFP - Trays |
| DS26504_06 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:T1/E1/J1/64KCC BITS Element |
| DS26504DK | 功能描述:网络开发工具 DS26504 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| DS26504L | 功能描述:计时器和支持产品 E1/T1/J1/64Kcc Bits Element RoHS:否 制造商:Micrel 类型:Standard 封装 / 箱体:SOT-23 内部定时器数量:1 电源电压-最大:18 V 电源电压-最小:2.7 V 最大功率耗散: 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装:Reel |
发布紧急采购，3分钟左右您将得到回复。