参数资料
型号: DS3112N
厂商: Maxim Integrated Products
文件页数: 64/133页
文件大小: 0K
描述: IC MUX TEMPE T3/E3 IND 256-BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
控制器类型: 调帧器,多路复用器
接口: 并行/串行
电源电压: 3.135 V ~ 3.465 V
电流 - 电源: 150mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-PBGA(27x27)
包装: 管件
DS3112
36 of 133
Register Name:
MC2
Register Description:
Master Configuration Register 2
Register Address:
04h
Bit #
7
6
5
4
3
2
1
0
Name
HTDATL
HTDATH
HRDATI
HRCLKI
HTDATI
HTCLKI
Default
0
Bit #
15
14
13
12
11
10
9
8
Name
LRDATI
LRCLKI
LTDATI
LTCLKI
Default
0
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0: HTCLK Invert Enable (HTCLKI).
0 = do not invert the HTCLK signal (normal mode)
1 = invert the HTCLK signal (inverted mode)
Bit 1: HTPOS/HTNEG Invert Enable (HTDATI).
0 = do not invert the HTPOS and HTNEG signals (normal mode)
1 = invert the HTPOS and HTNEG signals (inverted mode)
Bit 2: HRCLK Invert Enable (HRCLKI).
0 = do not invert the HRCLK signal (normal mode)
1 = invert the HRCLK signal (inverted mode)
Bit 3: HRPOS/HRNEG Invert Enable (HTDATI).
0 = do not invert the HRPOS and HRNEG signals (normal mode)
1 = invert the HRPOS and HRNEG signals (inverted mode)
Bit 4: HTPOS/HTNEG Force High Disable (HTDATH). Note that this bit must be set by the host in order for
T3/E3 traffic to be output from the device.
0 = force the HTPOS and HTNEG signals high (force high mode)
1 = allow normal transmit data to appear at the HTPOS and HTNEG signals (normal mode)
Bit 5: HTPOS/HTNEG Force Low Enable (HTDATL).
0 = allow normal transmit data to appear at the HTPOS and HTNEG signals (normal mode)
1 = force the HTPOS and HTNEG signals low (force low mode)
Bit 8: LTCLK Invert Enable (LTCLKI).
0 = do not invert the LTCLK[n], LTCLKA, LTCLKB, and LTCCLK signals (normal mode)
1 = invert the LTCLK[n], LTCLKA, LTCLKB, and LTCCLK signals (inverted mode)
Bit 9: LTDAT Invert Enable (LTDATI).
0 = do not invert the LTDAT[n], LTDATA and LTDATB signals (normal mode)
1 = invert the LTDAT[n], LTDATA and LTDATB signals (inverted mode)
Bit 10: LRCLK Invert Enable (LRCLKI).
0 = do not invert the LRCLK[n], LRCLKA, LRCLKB, and LRCCLK signals (normal mode)
1 = invert the LRCLK[n], LRCLKA, LRCLKB, and LRCCLK signals (inverted mode)
Bit 11: LRDAT Invert Enable (LRDATI).
0 = do not invert the LRDAT[n], LRDATA and LRDATB signals (normal mode)
1 = invert the LRDAT[n], LRDATA and LRDATB signals (inverted mode)
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DS3112RD 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流(最大值):595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray