参数资料
型号: DS3112N
厂商: Maxim Integrated Products
文件页数: 95/133页
文件大小: 0K
描述: IC MUX TEMPE T3/E3 IND 256-BGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 40
控制器类型: 调帧器,多路复用器
接口: 并行/串行
电源电压: 3.135 V ~ 3.465 V
电流 - 电源: 150mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 256-LBGA
供应商设备封装: 256-PBGA(27x27)
包装: 管件
DS3112
64 of 133
6.3 T2/E2/G.747 Framer Status and Interrupt Register Description
Register Name:
T2E2SR1
Register Description:
T2/E2 Status Register 1
Register Address:
34h
Bit #
7
6
5
4
3
2
1
0
Name
IELOF
LOF7
LOF6
LOF5
LOF4
LOF3
LOF2
LOF1
Default
0
-
Bit #
15
14
13
12
11
10
9
8
Name
IEAIS
AIS7
AIS6
AIS5
AIS4
AIS3
AIS2
AIS1
Default
0
-
Note: See Figure 6-1 for details on the signal flow for the status bits in the T2E2SR1 register. Bits that are underlined are read-only; all
other bits are read-write.
Bits 0 to 6: Loss Of Frame Occurrence (LOFn when n = 1 to 7). This latched read-only alarm-status bit will be
set to a one each time the corresponding T2/E2/G.747 framer detects a Loss Of Frame (LOF). This bit will be
cleared when read unless a LOF condition still exists in that T2/E2/G.747 framer. A change in state of the LOF in
one or more of the T2/E2/G.747 framers can cause the T2E2SR1 status bit (in the MSR register) to be set and a
hardware interrupt to occur if the IELOF bit is set to a one and the T2E2SR1 bit in the Interrupt Mask for MSR
(IMSR) register is set to a one (Figure 6-1). The interrupt will be allowed to clear when this bit is read. The LOF
alarm criteria are described in Table 6-1, Table 6-2, and Table 6-3. In the E3 mode, LOF5 to LOF7 (bits 4 to 6) are
meaningless and should be ignored.
Bit 7: Interrupt Enable for Loss of Frame Occurrence (IELOF). This bit should be set to one if the host wishes
to have T2/E2/G.747 LOF occurrences cause a hardware interrupt or the setting of the T2E2SR1 status bit in the
MSR register (Figure 6-1). The T2E2SR1 bit in the Interrupt Mask for the Master Status Register (IMSR) must
also be set to one for an interrupt to occur.
0 = interrupt masked
1 = interrupt unmasked
Bits 8 to 14: Alarm Indication Signal Detected (AISn when n = 1 to 7). This latched read-only alarm-status bit
will be set to a one each time the corresponding T2/E2/G.747 framer detects an incoming AIS alarm. This bit will
be cleared when read unless the AIS alarm still exists in that T2/E2/G.747 framer. A change in state of the AIS
detector in one or more of the T2/E2/G.747 framers can cause the T2E2SR1 status bit (in the MSR register) to be
set and a hardware interrupt to occur if the IEAIS bit is set to a one and the T2E2SR1 bit in the Interrupt Mask for
MSR (IMSR) register is set to a one (Figure 6-1). The interrupt will be allowed to clear when this bit is read. The
AIS alarm criteria is described in Table 6-1, Table 6-2, and Table 6-3. In the E3 mode, AIS5 to AIS7 (bits 4 to 6)
are meaningless and should be ignored.
Bit 15: Interrupt Enable for Alarm Indication Signal (IEAIS). This bit should be set to one if the host wishes to
have T2/E2/G.747 AIS detection occurrences cause a hardware interrupt or the setting of the T2E2SR1 status bit in
the MSR register (Figure 6-1). The T2E2SR1 bit in the Interrupt Mask for the Master Status Register (IMSR) must
also be set to one for an interrupt to occur.
0 = interrupt masked
1 = interrupt unmasked
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