参数资料
| 型号： | DS31412N |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 46/89页 |
| 文件大小： | 0K |
| 描述： | IC 12CH DS3/3 FRAMER 349-BGA |
| 标准包装： | 1 |
| 控制器类型： | DS3/E3 调帧器 |
| 接口： | LIU |
| 电源电压： | 3.135 V ~ 3.465 V |
| 电流 - 电源： | 960mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 349-BGA 裸露焊盘 |
| 供应商设备封装： | 349-HCBGA（27x27） |
| 包装： | 托盘 |
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DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
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Register Name:
BSRL
Register Description:
BERT Status Register Latched
Register Address:
39h
Bit #
7
6
5
4
3
2
1
0
Name
N/A
RA1L
RA0L
BEDL
BBCOL
BECOL
SYNCL
Default
—
Note: See Figure 7-6 for details on the interrupt logic for the status bits in the BSRL register.
Bit 0: Synchronization Status Latched (SYNCL). This latched status bit is set to 1 when the SYNC status bit in
the BSR register changes state (low to high or high to low). To determine if this bit was set because of finding
synchronization or losing synchronization, read the SYNC real-time status bit in the BSR register. SYNCL is
cleared when the host processor writes a 1 to it and is not set again until SYNC changes state again. When
SYNCL is set, it can cause a hardware interrupt to occur if the SYNCIE bit in the BSRIE register and the BERTIE
bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is cleared or one or both of the
interrupt-enable bits are cleared.
Bit 1: BERT Error-Counter Overflow Latched (BECOL). This latched status bit is set to 1 when the BECO status
bit in the BSR register goes high. BECOL is cleared when the host processor writes a one to it and is not set again
until BECO goes high again. When BECOL is set, it can cause a hardware interrupt to occur if the BECOIE bit in
the BSRIE register and the BERTIE bit in the MSRIE register are both set to a 1. The interrupt is cleared when this
bit is cleared or one or both of the interrupt-enable bits are cleared.
Bit 2: BERT Bit-Counter Overflow Latched (BBCOL). This latched status bit is set to 1 when the BBCO status bit
in the BSR register goes high. BBCOL is cleared when the host processor writes a 1 to it and is not set again until
BBCO goes high again. When BBCOL is set, it can cause a hardware interrupt to occur if the BBCOIE bit in the
BSRIE register and the BERTIE bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is
cleared or one or both of the interrupt-enable bits are cleared.
Bit 3: Bit Error-Detected Latched (BEDL). This latched status bit is set to 1 when a bit error is detected. The
receive BERT must be in synchronization to detect bit errors. BEDL is cleared when the host processor writes a 1
to it. When BEDL is set it can cause a hardware interrupt to occur if the BEDIE bit in the BSRIE register and the
BERTIE bit in the MSRIE register are both set to 1. The interrupt is cleared when this bit is cleared or one or both
of the interrupt-enable bits are cleared.
Bit 4: Receive All-Zeros Latched (RA0L). This latched status bit is set to 1 when the RA0 bit in the BSR register
is set. RA0L is cleared when the host processor writes a 1 to it. RA0L cannot cause an interrupt.
Bit 5: Receive All-Ones Latched (RA1L). This latched status bit is set to 1 when the RA1 bit in the BSR register is
set. RA1L is cleared when the host processor writes a 1 to it. RA1L cannot cause an interrupt.
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