参数资料
型号: DS31412N
厂商: Maxim Integrated Products
文件页数: 69/89页
文件大小: 0K
描述: IC 12CH DS3/3 FRAMER 349-BGA
标准包装: 1
控制器类型: DS3/E3 调帧器
接口: LIU
电源电压: 3.135 V ~ 3.465 V
电流 - 电源: 960mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 349-BGA 裸露焊盘
供应商设备封装: 349-HCBGA(27x27)
包装: 托盘
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
71 of 89
Figure 9-2. JTAG TAP Controller State Machine
Select-DR-Scan. All test registers retain their previous state. With JTMS low, a rising edge of JTCLK moves the
controller into the Capture-DR state and initiates a scan sequence. JTMS high moves the controller to the Select-
IR-SCAN state.
Capture-DR. Data can be parallel loaded into the test data registers selected by the current instruction. If the
instruction does not call for a parallel load or the selected register does not allow parallel loads, the test register
remains at its current value. On the rising edge of JTCLK, the controller goes to the Shift-DR state if JTMS is low or
to the Exit1-DR state if JTMS is high.
Shift-DR. The test data register selected by the current instruction is connected between JTDI and JTDO and shifts
data one stage toward its serial output on each rising edge of JTCLK. If a test register selected by the current
instruction is not placed in the serial path, it maintains its previous state.
Exit1-DR. While in this state, a rising edge on JTCLK with JTMS high puts the controller in the Update-DR state,
which terminates the scanning process. A rising edge on JTCLK with JTMS low puts the controller in the Pause-DR
state.
Pause-DR. Shifting of the test registers is halted while in this state. All test registers selected by the current
instruction retain their previous state. The controller remains in this state while JTMS is low. A rising edge on
JTCLK with JTMS high puts the controller in the Exit2-DR state.
Test-Logic-Reset
Run-Test/Idle
Select
DR-Scan
1
0
Capture-DR
1
0
Shift-DR
0
1
Exit1- DR
1
0
Pause-DR
1
Exit2-DR
1
Update-DR
0
1
Select
IR-Scan
1
0
Capture-IR
0
Shift-IR
0
1
Exit1-IR
1
0
Pause-IR
1
Exit2-IR
1
Update-IR
0
1
0
1
0
1
0
1
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