参数资料
型号: DS3251+
厂商: Maxim Integrated Products
文件页数: 38/71页
文件大小: 0K
描述: IC LIU DS3/E3/STS-1 144-CSBGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 160
类型: 线路接口装置(LIU)
驱动器/接收器数: 1/1
规程: DS3
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 144-BGA,CSPBGA
供应商设备封装: 144-TECSBGA(13x13)
包装: 托盘
产品目录页面: 1429 (CN2011-ZH PDF)
DS3251/DS3252/DS3253/DS3254
43 of 71
SAMPLE/PRELOAD. SAMPLE/RELOAD is a mandatory instruction for the IEEE 1149.1 specification. This
instruction supports two functions. The digital I/Os of the device can be sampled at the boundary scan register
without interfering with the device’s normal operation by using the Capture-DR state. SAMPLE/PRELOAD also
allows the DS325x to shift data into the boundary scan register through JTDI using the Shift-DR state.
EXTEST. EXTEST allows testing of the interconnections to the device. When the EXTEST instruction is latched in
the instruction register, the following actions occur. Once enabled through the Update-IR state, the parallel outputs
of the digital output pins are driven. The boundary scan register is connected between JTDI and JTDO. The
Capture-DR samples all digital inputs into the boundary scan register.
BYPASS. When the BYPASS instruction is latched into the parallel instruction register, JTDI connects to JTDO
through the 1-bit bypass test register. This allows data to pass from JTDI to JTDO without affecting the device’s
normal operation.
IDCODE. When the IDCODE instruction is latched into the parallel instruction register, the identification test
register is selected. The device identification code is loaded into the identification register on the rising edge of
JTCLK, following entry into the Capture-DR state. Shift-DR can be used to shift the identification code out serially
through JTDO. During Test-Logic-Reset, the identification code is forced into the instruction register’s parallel
output.
HIGHZ. All digital outputs are placed into a high-impedance state. The bypass register is connected between JTDI
and JTDO.
CLAMP. All digital output pins output data from the boundary scan parallel output while connecting the bypass
register between JTDI and JTDO. The outputs do not change during the CLAMP instruction.
Table 16-B. JTAG ID Code
PART
REVISION
DEVICE CODE
MANUFACTURER
CODE
REQUIRED
DS3251
Consult factory
0000000000101100
00010100001
1
DS3252
Consult factory
0000000000101101
00010100001
1
DS3253
Consult factory
0000000000101110
00010100001
1
DS3254
Consult factory
0000000000101111
00010100001
1
16.4 JTAG Test Registers
IEEE 1149.1 requires a minimum of two test registers—the bypass register and the boundary scan register. An
optional test register, the identification register, has been included in the device design. It is used with the IDCODE
instruction and the Test-Logic-Reset state of the TAP controller.
Bypass Register. This is a single 1-bit shift register used with the BYPASS, CLAMP, and HIGHZ instructions,
which provide a short path between JTDI and JTDO.
Boundary Scan Register. This register contains a shift register path and a latched parallel output for control cells
and digital I/O cells. DS325x BSDL files are available at www.maxim-ic.com/TechSupport/telecom/bsdl.htm.
Identification Register. This register contains a 32-bit shift register and a 32-bit latched parallel output. It is
selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-Reset state.
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DS32512A2 功能描述:网络控制器与处理器 IC 12-Port DS3/E3/STS-1 Line Interface Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流(最大值):595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray
DS32512DK 功能描述:网络开发工具 DS32512 Dev Kit RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V