参数资料
型号: DS3251+
厂商: Maxim Integrated Products
文件页数: 40/71页
文件大小: 0K
描述: IC LIU DS3/E3/STS-1 144-CSBGA
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 160
类型: 线路接口装置(LIU)
驱动器/接收器数: 1/1
规程: DS3
电源电压: 3.135 V ~ 3.465 V
安装类型: 表面贴装
封装/外壳: 144-BGA,CSPBGA
供应商设备封装: 144-TECSBGA(13x13)
包装: 托盘
产品目录页面: 1429 (CN2011-ZH PDF)
DS3251/DS3252/DS3253/DS3254
45 of 71
Table 17-C. Framer Interface Timing
(VDD = 3.3V ±5%, TA = -40°C to +85°C.) (Figure 17-1 and Figure 17-2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
(Note 1)
22.4
(Note 2)
29.1
RCLK/TCLK Clock Period
t1
(Note 3)
19.3
ns
RCLK Duty Cycle
t2/t1, t3/t1
(Notes 4, 5)
45
50
55
%
TCLK Duty Cycle
t2/t1, t3/t1
(Note 5)
30
70
%
MCLK Duty Cycle
t2/t1, t3/t1
(Note 5)
30
70
%
TPOS/TDAT, TNEG to TCLK Setup
Time
t4
(Notes 5, 6)
2
ns
TPOS/TDAT, TNEG Hold Time
t5
(Notes 5, 6)
2
ns
RCLK to RPOS/RDAT, RNEG/RLCV,
and PRBS Value Change
t6
(Notes 4, 5, 7)
2
6
ns
RCLK Rise and Fall Time
t7
(Notes 5, 8)
3
5
ns
TCLK Rise and Fall Time
t8
(Notes 5, 9)
5
ns
Note 1:
DS3 mode.
Note 2:
E3 mode.
Note 3:
STS-1 mode.
Note 4:
Outputs loaded with 25pF, measured at 50% threshold.
Note 5:
Not tested during production test.
Note 6:
When TCINV = 0, TPOS/TDAT and TNEG are sampled on the rising edge of TCLK. When TCINV = 1, TPOS/TDAT and TNEG
are sampled on the falling edge of TCLK.
Note 7:
When RCINV = 0, RPOS/RDAT and RNEG/RLCV are updated on the falling edge of RCLK. When RCINV = 1, RPOS/RDAT and
RNEG/RLCV are updated on the rising edge of RCLK.
Note 8:
Outputs loaded with 25pF, measured between VOL (max) and VOH (min).
Note 9:
Measured between VIL (max) and VIH (min).
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