DS3911
Temperature-Controlled, Nonvolatile,
I2C Quad DAC
11
Maxim Integrated
how a positive and negative tempco can be achieved by
after each temperature conversion.
The LUT features 1NC hysteresis to prevent chatter-
ing if the measured temperature falls on the boundary
implemented in the
TINDEX register value calculation by
adding 1NC to temperature changes of negative slope.
Temperature Conversion and
Supply Voltage Monitoring
Temperature Conversion
The device features an internal 12-bit temperature sensor
that can drive the LUT and provide a measurement of the
ambient temperature over I2C by reading the value stored
in memory addresses 04h–05h. The sensor is functional
over the entire operating temperature range, and the results
are stored in signed two’s-complement format with a 1/16NC
VALUE section for the temperature sensor’s bit weights. The
DONETEMP bit located in the
CTRL register indicates
whether a temperature conversion has been completed
since the bit was last cleared.
Supply Voltage Monitoring
The device also features an internal 13-bit supply voltage
(VCC) monitor. A left-justified value of the supply voltage
measurement can be read over I2C at memory address-
es 06h–07h. To calculate the supply voltage, simply
convert the hexadecimal result into decimal and then
The DONEVCC bit located in the
CTRL register indicates
whether a VCC conversion has been completed since the
bit was last cleared.
Slave Address Byte and Address Pins
The slave address byte consists of a 7-bit slave address
plus a R/W bit, as shown in
Figure 6. The device’s slave
address is determined by the state of the A0 and A1
address pins. These pins allow up to four devices to
reside on the same I2C bus. Address pins connected to
GND result in a 0 in the corresponding bit position in the
slave address. Conversely, address pins connected to
VCC result in a 1 in the corresponding bit positions. For
example, the device’s slave address byte is B0h when
section for more information.
I2C Serial Interface
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers. See the timing diagram (Figure 1) and information.
Master Device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states.
START Condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition.
Figure 5. LUT Hysteresis
Figure 6. DS3911 Slave Address Byte
MEMORY
LOCATION
9D
DECREASING
TEMPERATURE
INCREASING
TEMPERATURE
1°C HYSTERESIS
WINDOW
TEMPERATURE (°C)
56
58
60
62
64
66
9C
9B
9A
99
98
10
1
1R/W
A0
A1
0
MSB
LSB
SLAVE ADDRESS*
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
READ/WRITE BIT