参数资料
| 型号： | DS3911T+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 4/24页 |
| 文件大小： | 0K |
| 描述： | IC DAC 10BIT I2C QUAD 14TDFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 100 |
| 位数： | 10 |
| 数据接口： | I²C，串行 |
| 转换器数目： | 4 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 1.74W |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-WFDFN 裸露焊盘 |
| 供应商设备封装： | 14-TDFN-EP（3x5） |
| 包装： | 管件 |
| 输出数目和类型： | 4 电压，单极 |
| 采样率（每秒）： | * |
DS3911
Temperature-Controlled, Nonvolatile,
I2C Quad DAC
12
Maxim Integrated
STOP Condition: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition.
Repeated START Condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTs
are commonly used during read operations to identify
a specific memory address to begin a data transfer.
A repeated START condition is issued identically to a
normal START condition.
Bit Write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into
the device during the rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA
at the falling edge of the previous SCL pulse and the
data bit is valid at the rising edge of the current SCL
pulse. Remember that the master generates all SCL
clock pulses including when it is reading bits from the
slave.
Acknowledge (ACK and NACK): An acknowledge
(ACK) or not-acknowledge (NACK) is always the 9th bit
transmitted during a byte transfer. The device receiv-
ing data (the master during a read or the slave during
a write operation) performs an ACK by transmitting a
zero during the 9th bit. A device performs a NACK by
transmitting a one (done by releasing SDA) during the
9th bit. Timing for the ACK and NACK is identical to all
other bit writes. An ACK is the acknowledgment that
the device is properly receiving data (see Figure 7). A
NACK is used to terminate a read sequence, or used
as an indication that the device is not receiving data.
Byte Write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most sig-
nificant bit first) plus a 1-bit acknowledgment from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgment is read using the bit read definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave returns control of SDA to
the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
The device’s slave address is determined by the state
of the A0 and A1 address pins as shown in Figure 6.
Address pins connected to GND result in a 0 in the corre-
sponding bit position in the slave address. Conversely,
address pins connected to VCC result in a 1 in the
corresponding bit positions. When the R/W bit is 0
(such as in B0h), the master is indicating it will write
data to the slave. If R/W is set to 1 (B1h in this case),
the master is indicating it wants to read from the slave.
If an incorrect (nonmatching) slave address is written,
the device assumes the master is communicating with
another I2C device and ignores the communication
until the next START condition is sent.
Memory Address: During an I2C write operation to the
device, the master must transmit a memory address to
identify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following the
slave address byte.
I2C Communication
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write the
byte of data, and generate a STOP condition. The mas-
ter must read the slave’s acknowledgement during all
byte write operations.
When writing to the device, the DAC’s output adjusts
to the new setting once it has acknowledged the new
data that is being written, and writes to the EEPROM
are written following the STOP condition at the end of
the write command.
Writing Multiple Bytes to a Slave: I2C write opera-
tions of multiple bytes can also be performed. During
a single write sequence, up to 8 bytes in one page
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| DS3911T+ | 功能描述:ADC / DAC多通道 Fast APD Bias RoHS:否 制造商:Texas Instruments 转换速率: 分辨率:8 bit 接口类型:SPI 电压参考: 电源电压-最大:3.6 V 电源电压-最小:2 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-40 |
| DS3911T+T | 功能描述:ADC / DAC多通道 Fast APD Bias RoHS:否 制造商:Texas Instruments 转换速率: 分辨率:8 bit 接口类型:SPI 电压参考: 电源电压-最大:3.6 V 电源电压-最小:2 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-40 |
| DS3920 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Fast Current Mirror |
| DS3920_1112 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:Fast Current Mirror |
| DS3920T-001+ | 功能描述:电流和电力监控器、调节器 Fast APD Bias RoHS:否 制造商:STMicroelectronics 产品:Current Regulators 电源电压-最大:48 V 电源电压-最小:5.5 V 工作温度范围:- 40 C to + 150 C 安装风格:SMD/SMT 封装 / 箱体:HPSO-8 封装:Reel |
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