参数资料
型号: DS4830T+T
厂商: Maxim Integrated Products
文件页数: 14/30页
文件大小: 0K
描述: MCU 16B CTRL CALIBR MON 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: MAXQ®
核心处理器: RISC
芯体尺寸: 16-位
速度: 10MHz
连通性: 3 线,I²C,SPI
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 31
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
RAM 容量: 1K x 16
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 18x13b,D/A 8x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 16-WQFN 裸露焊盘
包装: 带卷 (TR)
其它名称: 90-4830T+TRL
DS4830
Optical Microcontroller
21
Maxim Integrated
allows the application to develop custom loader software
that can operate under the control of the application soft-
ware. The utility ROM contains firmware-accessible flash
programming functions that erase and program flash
memory. These functions are described in detail in the
DS4830 User’s Guide.
Register Set
Sets of registers control most device functions. These
registers provide a working space for memory opera-
tions as well as configuring and addressing peripheral
registers on the device. Registers are divided into two
major types: system registers (special-purpose registers,
or SPRs) and peripheral registers (special-function reg-
isters, or SFRs). The common register set, also known
as the system registers, includes the ALU, accumulator
registers, data pointers, interrupt vectors and control,
and stack pointer. The peripheral registers define addi-
tional functionality, and the functionality is broken up
into discrete modules. Both the system registers and the
peripheral registers are described in detail in the DS4830
User’s Guide.
System Timing
The device generates its 10MHz instruction clock
(MOSC) internally. On power-up, the oscillator’s output
(which cannot be accessed externally) is disabled until
VDD rises above VBO. Once this threshold is reached, the
output is enabled after approximately 1ms, clocking the
device. See Figure 8.
System Reset
The device features several sources that can be used to
reset the DS4830.
Power-On Reset
An internal power-on-reset (POR) circuit is used to
enhance system reliability. This circuit forces the device
to perform a POR whenever a rising voltage on VDD
climbs above VBO. When this happens the following
events occur:
Allregistersandcircuitsentertheirresetstate.
ThePORflag(WDCN.7)issettoindicatethesource
of the reset.
Code execution begins at location 8000h when the
reset condition is released.
Brownout Detect/Reset
The device features a brownout detect/reset function.
Whenever the power monitor detects a brownout condi-
tion (when VDD < VBO), it immediately issues a reset and
stays in that state as long as VDD remains below VBO.
Once VDD voltage rises above VBO, the device waits
for tSU:MOSC before returning to normal operation, also
referred to as CPU state. If a brownout occurs during
tSU:MOSC, the device again goes back to the brownout
state. Otherwise, it enters into CPU state. In CPU state,
the brownout detector is also enabled.
On power-up, the device always enters brownout state
first and then follows the above sequence. The reset
issued by brownout is the same as POR. Any action
performed after POR also happens on brownout reset.
Figure 8. System Timing
tSU:MOSC = ~1ms
CORE
CLOCK
VDD
VBO
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