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| 型号： | DS4830T+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/30页 |
| 文件大小： | 0K |
| 描述： | MCU 16B CTRL CALIBR MON 40-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | MAXQ® |
| 核心处理器： | RISC |
| 芯体尺寸： | 16-位 |
| 速度： | 10MHz |
| 连通性： | 3 线，I²C，SPI |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 31 |
| 程序存储器容量： | 64KB（32K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 16 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 18x13b，D/A 8x12b |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 16-WQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 其它名称： | 90-4830T+TRL |
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DS4830
Optical Microcontroller
22
Maxim Integrated
All the registers that are cleared on POR are also cleared
on brownout reset.
Watchdog Timer Reset
The watchdog timer provides a mechanism to reset the
processor in the case of undesirable code execution. The
watchdog timer is a hardware timer designed to be peri-
odically reset by the application software. If the software
operates correctly, the timer is reset before it reaches its
maximum count. However, if undesirable code execution
prevents a reset of the watchdog timer, the timer reaches
its maximum count and resets the processor.
The watchdog timer is controlled through two bits in the
WDCN register (WDCN[5:4]: WD[1:0]). Its timeout period
can be set to one of the four programmable intervals
ranging from 212 to 221 system clock (MOSC) periods
(0.409ms to 0.210s). The watchdog interrupt occurs at
the end of this timeout period, which is 512 MOSC clock
periods, or approximately 50Fs, before the reset. The
reset generated by the watchdog timer lasts for four sys-
tem clock cycles, which is 0.4Fs. Software can determine
if a reset is caused by a watchdog timeout by checking
the watchdog timer reset flag (WTRF) in the WDCN reg-
ister. Execution resumes at location 8000h following a
watchdog timer reset.
External Reset
Asserting RST low causes the device to enter the reset
state. The external reset function is described in the
DS4830 User’s Guide. Execution resumes at location
8000h after RST is released. The DAC and PWM outputs
are unchanged during execution of external reset.
Internal System Reset
The host can issue an I2C command (BBh) to reset the
communicating device. This reset has the same effect as
the external reset as far as the reset values of all registers
are concerned. Also, an internal system reset can occur
when the in-system programming is done (ROD = 1). The
DAC and PWM outputs are unchanged during execution
of an internal reset.
Further details are available in the DS4830 User’s Guide.
Programmable Timer
The device features two general-purpose programmable
timers. Various timing loops can be implemented using the
timers. Each general-purpose timer uses three SFRs. GTCN
is the general control register, GTV is the timer value regis-
ter, and GTC is the timer compare register.
The timer can be used in two modes: free-running mode
and compare mode with interrupts. Both are described in
detail in the DS4830 User’s Guide.
The functionality of the timers can be accessed through
three SFRs for each of the general-purpose timers. The
timer SFRs are accessed in module 0 and module 3.
Detailed information regarding the timer block can be
found in the DS4830 User’s Guide.
Hardware Multiplier
The hardware multiplier (multiply-accumulate, or MAC
module) is a very powerful tool, especially for applica-
tions that require heavy calculations. This multiplier
can execute the multiply or multiply-negate, or multiply-
accumulate or multiply-subtract operation for signed or
unsigned operands. The MAC module uses eight SFRs,
mapped as register 0h–05h and 08h–09h in module M3.
System Interrupts
Multiple interrupt sources are available to respond to
internal and external events. The microcontroller archi-
tecture uses a single interrupt vector (IV) and single
interrupt-service routine (ISR) design. For maximum flex-
ibility, interrupts can be enabled globally, individually, or
by module. When an interrupt condition occurs, its indi-
vidual flag is set, even if the interrupt source is disabled
at the local, module, or global level. Interrupt flags must
be cleared within the firmware-interrupt routine to avoid
repeated interrupts from the same source. Application
software must ensure a delay between the write to the
flag and the RETI instruction to allow time for the inter-
rupt hardware to remove the internal interrupt condition.
Asynchronous interrupt flags require a one-instruction
delay and synchronous interrupt flags require a two-
instruction delay.
When an enabled interrupt is detected, execution jumps
to a user-programmable interrupt vector location. The IV
register defaults to 0000h on reset or power-up, so if it is
not changed to a different address, application firmware
must determine whether a jump to 0000h came from a
RST or interrupt source.
Once control has been transferred to the ISR, the inter-
rupt identification register (IIR) can be used to determine
if a system register or peripheral register was the source
of the interrupt. In addition to IIR, MIIR registers are
implemented to indicate which particular function under
a peripheral module has caused the interrupt. The device
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| DS485M | 功能描述:RS-422/RS-485 接口 IC RoHS:否 制造商:Maxim Integrated 数据速率:1136 Kbps 工作电源电压:3 V to 5.5 V 电源电流:5.9 mA 工作温度范围:- 40 C to + 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-28 封装:Tube |
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