参数资料
型号: DS4830T+T
厂商: Maxim Integrated Products
文件页数: 29/30页
文件大小: 0K
描述: MCU 16B CTRL CALIBR MON 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: MAXQ®
核心处理器: RISC
芯体尺寸: 16-位
速度: 10MHz
连通性: 3 线,I²C,SPI
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 31
程序存储器容量: 64KB(32K x 16)
程序存储器类型: 闪存
RAM 容量: 1K x 16
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 18x13b,D/A 8x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 16-WQFN 裸露焊盘
包装: 带卷 (TR)
其它名称: 90-4830T+TRL
DS4830
Optical Microcontroller
8
Maxim Integrated
SPI DIGITAL InTERFACE SPECIFICATIOn (continued)
(VDD = 2.97V to 3.63V, TA = -40NC to +85NC, unless otherwise noted.) (See Figure 3 and Figure 4.)
ELECTRICAL CHARACTERISTICS: JTAG InTERFACE
(VDD = 2.97V to 3.63V, TA = -40NC to +85NC, unless otherwise noted.) (Figure 5)
note 1: All voltages are referenced to GND. Currents entering the IC are specified as positive, and currents exiting the IC are
specified as negative.
note 2: Maximum current assuming 100% CPU duty cycle.
note 3: This value does not include current in GPIO, SCL, SDA, MDIO, MDI, MCL, REFINA, and REFINB.
note 4: Using internal reference.
note 5: There is one internal oscillator. The oscillator (peripheral clock) goes through a 2:1 divider to create the core clock.
note 6: Guaranteed by design.
note 7: ADC conversions are delayed up to 1.6Fs if the fast comparator is sampling the selected ADC channel. This can cause a
slight decrease in the ADC sampling rate.
note 8: Temperature readings average 64 times.
note 9: Programming time does not include overhead associated with the utility ROM interface.
note 10: fSCL must meet the minimum clock low time plus the rise/fall times.
note 11: This device internally provides a hold time of at least 75ns for the SDA signal (referred to the VIH:MIN of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
note 12: CB—Total capacitance of one bus line in pF.
note 13: Filters on SDA and SCL suppress noise spikes at the input buffers and delay the sampling instant.
PARAMETER
SYMBOL
COnDITIOnS
MIn
TYP
MAx
UnITS
SSPIDO Output Valid After
SSPICK Shift Edge Transition
tSOV
2tSPI_RF
ns
SSPICS Inactive
tSSH
tSSPICK +
tSPI_RF
ns
SSPICK Inactive to SSPICS
Rising
tSD
tSPI_RF
ns
SSPIDO Output Disabled After
SSPICS Edge Rise
tSLH
2tSSPICK
+
2tSPI_RF
ns
PARAMETER
SYMBOL
COnDITIOnS
MIn
TYP
MAx
UnITS
JTAG Logic Reference
VREF
VDD/2
V
TCK High Time
tTH
0.5
F
s
TCK Low Time
tTL
0.5
F
s
TCK Low to TDO Output
tTLQ
0.125
F
s
TMS, TDI Input Setup to TCK High
tDVTH
0.25
F
s
TMS, TDI Input Hold After TCK
High
tTHDX
0.25
F
s
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