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参数资料
| 型号： | DSP56855BUE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 22/52页 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 120MHZ 100-LQFP |
| 标准包装： | 90 |
| 系列： | 568xx |
| 核心处理器： | 56800E |
| 芯体尺寸： | 16-位 |
| 速度： | 120MHz |
| 连通性： | EBI/EMI，SCI，SSI |
| 外围设备： | DMA，POR，WDT |
| 输入/输出数： | 18 |
| 程序存储器容量： | 48KB（24K x 16） |
| 程序存储器类型： | SRAM |
| RAM 容量： | 24K x 16 |
| 电压 - 电源 (Vcc/Vdd)： | 1.62 V ~ 1.98 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 包装： | 托盘 |
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Reset, Stop, Wait, Mode Select, and Interrupt Timing
56855 Technical Data, Rev. 6
Freescale Semiconductor
29
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM
18T
—
ns
tIDM -FAST
14T
—
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
18T
—
ns
tIG -FAST
14T
—
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State4
tIRI
22T
—
ns
tIRI -FAST
18T
—
Delay from IRQA Assertion (exiting Stop) to External
Data Memory5
tIW
1.5T
—
ns
Delay from IRQA Assertion (exiting Wait) to External
Data Memory
Fast6
Normal7
tIF
18T
22ET
—
ns
RSTO pulse width8
normal operation
internal reset mode
tRSTO
128ET
8ET
—
1. In the formulas, T = clock cycle. For fop = 120MHz operation and fipb = 60MHz, T = 8.33ns.
2. Parameters listed are guaranteed by design.
3. At reset, the PLL is disabled and bypassed. The part is then put into Run mode and tclk assumes the period of the source clock,
txtal, textal or tosc.
4. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not
the minimum required so that the IRQA interrupt is accepted.
5. The interrupt instruction fetch is visible on the pins only in Mode 3.
6. Fast stop mode:
Fast stop recovery applies when external clocking is in use (direct clocking to XTAL) or when fast stop mode recovery is re-
quested (OMR bit 6 is set to 1). In both cases the PLL and the master clock are unaffected by stop mode entry. Recovery takes one
less cycle and tclk will continue same value it had before stop mode was entered.
7. Normal stop mode:
As a power saving feature, normal stop mode disables and bypasses the PLL. Stop mode will then shut down the master clock,
recovery will take an extra cycle (to restart the clock), and tclk will resume at the input clock source rate.
8. ET = External Clock period, For an external crystal frequency of 8MHz, ET=125 ns.
Table 1. Reset, Stop, Wait, Mode Select, and Interrupt Timing1, 2 (Continued)
Operating Conditions: VSS = VSSIO = VSSA = 0 V, VDD = 1.62-1.98V, VDDIO = VDDA = 3.0–3.6V, TA = –40° to +120°C, CL ≤ 50pF, fop = 120MHz
Characteristic
Symbol
Min
Max
Unit
See Figure
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DSP56855E | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56855PB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:56855 Digital Signal Processor Product Brief |
| DSP56856 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Digitial Signal Controller |
| DSP56857 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56857BU120 | 功能描述:数字信号处理器和控制器 - DSP, DSC 120Mhz/120MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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