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参数资料
| 型号： | DSP56855BUE |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 9/52页 |
| 文件大小： | 0K |
| 描述： | IC DSP 16BIT 120MHZ 100-LQFP |
| 标准包装： | 90 |
| 系列： | 568xx |
| 核心处理器： | 56800E |
| 芯体尺寸： | 16-位 |
| 速度： | 120MHz |
| 连通性： | EBI/EMI，SCI，SSI |
| 外围设备： | DMA，POR，WDT |
| 输入/输出数： | 18 |
| 程序存储器容量： | 48KB（24K x 16） |
| 程序存储器类型： | SRAM |
| RAM 容量： | 24K x 16 |
| 电压 - 电源 (Vcc/Vdd)： | 1.62 V ~ 1.98 V |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 包装： | 托盘 |
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General Characteristics
56855 Technical Data, Rev. 6
Freescale Semiconductor
17
Part 4 Specifications
4.1 General Characteristics
The 56855 is fabricated in high-density CMOS with 5-volt tolerant TTL-compatible digital inputs. The
term “5-volt tolerant” refers to the capability of an I/O pin, built on a 3.3V compatible process
technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a
mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V
and 5V- compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of
3.3V
± 10% during normal operation without causing damage). This 5V tolerant capability therefore
offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged.
Absolute maximum ratings given in Table 4-1 are stress ratings only, and functional operation at the
maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent
damage to the device.
The 56855 DC/AC electrical specifications are preliminary and are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
41
TMS
Input
Test Mode Select Input (TMS)—This input pin is used to sequence the
JTAG TAP controller’s state machine. It is sampled on the rising edge of
TCK and has an on-chip pull-up resistor.
Note:
Always tie the TMS pin to VDD through a 2.2K resistor.
38
TRST
Input
Test Reset (TRST)—As an input, a low signal on this pin provides a reset
signal to the JTAG TAP controller. To ensure complete hardware reset,
TRST should be asserted whenever RESET is asserted. The only
exception occurs in a debugging environment, since the Enhanced
OnCE/JTAG module is under the control of the debugger. In this case it is
not necessary to assert TRST when asserting RESET. Outside of a
debugging environment RESET should be permanently asserted by
grounding the signal, thus disabling the Enhanced OnCE/JTAG module on
the device.
Note:
For normal operation, connect TRST directly to VSS. If the design is to be
used in a debugging environment, TRST may be tied to VSS through a 1K resistor.
37
DE
Input/Output
Debug Event (DE)—This is an open-drain, bidirectional, active low signal.
As an input, it is a means of entering debug mode of operation from an
external command controller. As an output, it is a means of acknowledging
that the chip has entered debug mode.
This pin is connected internally to a weak pull-up resistor.
Table 3-1. 56855 Signal and Package Information for the 100-pin LQFP (Continued)
Pin No.
Signal Name
Type
Description
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DSP56855E | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56855PB | 制造商:未知厂家 制造商全称:未知厂家 功能描述:56855 Digital Signal Processor Product Brief |
| DSP56856 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Digitial Signal Controller |
| DSP56857 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56857BU120 | 功能描述:数字信号处理器和控制器 - DSP, DSC 120Mhz/120MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 数据总线宽度:16 bit 程序存储器大小:16 KB 数据 RAM 大小:2 KB 最大时钟频率:40 MHz 可编程输入/输出端数量:35 定时器数量:3 设备每秒兆指令数:50 MIPs 工作电源电压:3.3 V 最大工作温度:+ 85 C 封装 / 箱体:TQFP-44 安装风格:SMD/SMT |
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