参数资料
型号: DSP56855BUE
厂商: Freescale Semiconductor
文件页数: 23/52页
文件大小: 0K
描述: IC DSP 16BIT 120MHZ 100-LQFP
标准包装: 90
系列: 568xx
核心处理器: 56800E
芯体尺寸: 16-位
速度: 120MHz
连通性: EBI/EMI,SCI,SSI
外围设备: DMA,POR,WDT
输入/输出数: 18
程序存储器容量: 48KB(24K x 16)
程序存储器类型: SRAM
RAM 容量: 24K x 16
电压 - 电源 (Vcc/Vdd): 1.62 V ~ 1.98 V
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
56855 Technical Data, Rev. 6
Freescale Semiconductor
3
56855 Block Diagram
JTAG/
Enhanced
OnCE
Program Controller
and
Hardware Looping Unit
Data ALU
16 x 16 + 36
→ 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
Address
Generation Unit
Bit
Manipulation
Unit
16-Bit
DSP56800E Core
XTAL
EXTAL
Interrupt
Controller
Quad
Timer
or
GPIOG
4
CLKO
External Address
Bus Switch
External Bus
Interface Unit
RESET
IRQA
IRQB
VDD VSSIO
VDDA VSSA
External Data
Bus Switch
Bus Control
WR Enable
RD Enable
CS0-CS3[3:0] or
A0-20 [20:0]
MODEA-C or
D0-D15 [15:0]
6
Program Memory
24,576 x 16 SRAM
Boot ROM
1024 x 16 ROM
Data Memory
24,576 x 16 SRAM
PDB
XAB1
XAB2
XDB2
CDBR
2 SCI
or
GPIOE
IPBus Bridge (IPBB)
3
(GPIOH0-H2)
4
10
VDDIO
10
Decoding
Peripherals
System
Bus
Control
Memory
PAB
CDBW
CDBR
CDBW
VSS
4
GPIOA0-GPIOA3[3:0]
6
ESSI0
or
GPIOC
RSTO
DMA
6 channel
POR
Integration
Module
System
COP/
Watch-
dog
Time
of
Day
Clock
Generator
OSC PLL
IPBus CLK
COP/TOD CLK
Core CLK
IP
A
B
IPW
D
B
IPRDB
DMA
Req
ues
ts
56855 General Description
120 MIPS at 120MHz
24K x 16-bit Program SRAM
24K x 16-bit Data SRAM
1K x 16-bit Boot ROM
Access up to 2M words of program memory or 8M
words of data memory
Chip Select Logic for glueless interface to ROM and
SRAM
Six (6) independent channels of DMA
Enhanced Synchronous Serial Interface (ESSI)
Two (2) Serial Communication Interfaces (SCI)
General Purpose 16-bit Quad Timer with 1 external pin
JTAG/Enhanced On-Chip Emulation (OnCE) for
unobtrusive, real-time debugging
Computer Operating Properly (COP)/Watchdog Timer
Time-of-Day (TOD)
100 LQFP package
Up to 18 GPIO
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