参数资料
型号: DSP56F803BU80E
厂商: Freescale Semiconductor
文件页数: 15/52页
文件大小: 0K
描述: IC DSP 80MHZ 64KB FLASH 100LQFP
特色产品: DSP56F803 Digital Signal Controller
标准包装: 90
系列: 56F8xx
核心处理器: 56800
芯体尺寸: 16-位
速度: 80MHz
连通性: CAN,EBI/EMI,SCI,SPI
外围设备: POR,PWM,WDT
输入/输出数: 16
程序存储器容量: 71KB(35.5K x 16)
程序存储器类型: 闪存
RAM 容量: 2.5K x 16
电压 - 电源 (Vcc/Vdd): 3 V ~ 3.6 V
数据转换器: A/D 8x12b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 100-LQFP
包装: 托盘
56F803 Technical Data, Rev. 16
22
Freescale Semiconductor
Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-14)
3.3 AC Electrical Characteristics
Timing waveforms in Section 3.3 are tested using the V
IL and VIH levels specified in the DC Characteristics
table. In Figure 3-2 the levels of V
IH and VIL for an input signal are shown.
8.
This low-voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential
as VDD via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed
under transient conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is
generated).
9.
This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is
regulator drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not
be generated unless the external power supply drops below the minimum specified value (3.0V).
10. Power
on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is
ramping up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate
is. The internally regulated voltage is typically 100mV less than VDD during ramp-up, until 2.5V is reached, at which time it
self-regulates.
0
30
90
120
180
60
20
40
60
80
Freq. (MHz)
IDD
(mA)
150
IDD Digital
IDD Analog
IDD Total
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