- 您现在的位置：买卖IC网 > PDF目录1917 > DSP56F803BU80E (Freescale Semiconductor)IC DSP 80MHZ 64KB FLASH 100LQFP PDF资料下载
参数资料
| 型号： | DSP56F803BU80E |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 27/52页 |
| 文件大小： | 0K |
| 描述： | IC DSP 80MHZ 64KB FLASH 100LQFP |
| 特色产品： | DSP56F803 Digital Signal Controller |
| 标准包装： | 90 |
| 系列： | 56F8xx |
| 核心处理器： | 56800 |
| 芯体尺寸： | 16-位 |
| 速度： | 80MHz |
| 连通性： | CAN，EBI/EMI，SCI，SPI |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 16 |
| 程序存储器容量： | 71KB（35.5K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2.5K x 16 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页
Reset, Stop, Wait, Mode Select, and Interrupt Timing
56F803 Technical Data, Rev. 16
Freescale Semiconductor
33
Edge-sensitive Interrupt Request Width
tIRW
1.5T
—
ns
IRQA, IRQB Assertion to External Data Memory
Access Out Valid, caused by first instruction execution
in the interrupt service routine
tIDM
15T
—
ns
IRQA, IRQB Assertion to General Purpose Output
Valid, caused by first instruction execution in the
interrupt service routine
tIG
16T
—
ns
IRQA Low to First Valid Interrupt Vector Address Out
recovery from Wait State3
tIRI
13T
—
ns
IRQA Width Assertion to Recover from Stop State4
tIW
2T
—
ns
Delay from IRQA Assertion to Fetch of first instruction
(exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIF
—
275,000T
12T
ns
Duration for Level Sensitive IRQA Assertion to Cause
the Fetch of First IRQA Interrupt Instruction (exiting
Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tIRQ
—
275,000T
12T
ns
Delay from Level Sensitive IRQA Assertion to First
Interrupt Vector Address Out Valid (exiting Stop)
OMR Bit 6 = 0
OMR Bit 6 = 1
tII
—
275,000T
12T
ns
1.
In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns.
2.
Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases:
After power-on reset
When recovering from Stop state
3.
The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is
not the minimum required so that the IRQA interrupt is accepted.
4.
The interrupt instruction fetch is visible on the pins only in Mode 3.
5.
Parameters listed are guaranteed by design.
Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing (Continued)1, 5
Operating Conditions: V
SS = VSSA = 0 V, VDD = VDDA = 3.0–3.6V, TA = –40° to +85°C, CL ≤ 50pF
Characteristic
Symbol
Min
Max
Unit
See Figure
相关PDF资料 |
PDF描述 |
|---|---|
| DSP56F805FV80E | IC DSP 80MHZ 64KB FLASH 144LQFP |
| DSP56F807VF80E | IC DSP 80MHZ 60K FLASH 160-BGA |
| DSP56F826BU80 | IC DSP 80MHZ 64KB FLASH 100LQFP |
| DSP56F827FG80E | IC HYBRID CTRLR 16BIT 128-LQFP |
| DSPB56362AG120 | IC DSP 24BIT AUD 120MHZ 144-LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DSP56F803BU80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSP56F803BU80E | 制造商:Freescale Semiconductor 功能描述:DSP LQFP100 3.6V |
| DSP56F803E | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56F803EVM | 功能描述:开发板和工具包 - 其他处理器 Evaluation Kit For DSP56F803 RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| DSP56F803EVMUM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:56F803 Evaluation Module Hardware User＇s Manual |
发布紧急采购，3分钟左右您将得到回复。