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| 型号： | DSP56F803BU80E |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 3/52页 |
| 文件大小： | 0K |
| 描述： | IC DSP 80MHZ 64KB FLASH 100LQFP |
| 特色产品： | DSP56F803 Digital Signal Controller |
| 标准包装： | 90 |
| 系列： | 56F8xx |
| 核心处理器： | 56800 |
| 芯体尺寸： | 16-位 |
| 速度： | 80MHz |
| 连通性： | CAN，EBI/EMI，SCI，SPI |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 16 |
| 程序存储器容量： | 71KB（35.5K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2.5K x 16 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 包装： | 托盘 |
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Clock and Phase Locked Loop Signals
56F803 Technical Data, Rev. 16
Freescale Semiconductor
11
2.3 Clock and Phase Locked Loop Signals
2.4 Address, Data, and Bus Control Signals
Table 2-5 PLL and Clock
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
EXTAL
Input
External Crystal Oscillator Input—This input should be connected to
an 8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.5.
1
XTAL
Input/
Output
Chip-driven
Crystal Oscillator Output—This output should be connected to an
8MHz external crystal or ceramic resonator. For more information,
please refer to Section 3.5.
This pin can also be connected to an external clock source. For more
information, please refer to Section 3.5.3.
1
CLKO
Output
Chip-driven
Clock Output—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select Register
(CLKOSR), the user can select between outputting a version of the
signal applied to XTAL and a version of the device’s master clock at the
output of the PLL. The clock frequency on this pin can also be disabled
by programming the CLKOSEL[4:0] bits in CLKOSR.
Table 2-6 Address Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
A0–A5
Output
Tri-stated
Address Bus—A0–A5 specify the address for external Program or Data
memory accesses.
2
A6–A7
GPIOE2–
GPIOE3
Output
Input/O
utput
Tri-stated
Input
Address Bus—A6–A7 specify the address for external Program or Data
memory accesses.
Port E GPIO—These two pins are General Purpose I/O (GPIO) pins that
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15
GPIOA0–
GPIOA7
Output
Input/O
utput
Tri-stated
Input
Address Bus—A8–A15 specify the address for external Program or
Data memory accesses.
Port A GPIO—These eight pins are General Purpose I/O (GPIO) pins
that can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DSP56F803BU80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSP56F803BU80E | 制造商:Freescale Semiconductor 功能描述:DSP LQFP100 3.6V |
| DSP56F803E | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56F803EVM | 功能描述:开发板和工具包 - 其他处理器 Evaluation Kit For DSP56F803 RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| DSP56F803EVMUM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:56F803 Evaluation Module Hardware User＇s Manual |
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