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| 型号： | DSP56F803BU80E |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 4/52页 |
| 文件大小： | 0K |
| 描述： | IC DSP 80MHZ 64KB FLASH 100LQFP |
| 特色产品： | DSP56F803 Digital Signal Controller |
| 标准包装： | 90 |
| 系列： | 56F8xx |
| 核心处理器： | 56800 |
| 芯体尺寸： | 16-位 |
| 速度： | 80MHz |
| 连通性： | CAN，EBI/EMI，SCI，SPI |
| 外围设备： | POR，PWM，WDT |
| 输入/输出数： | 16 |
| 程序存储器容量： | 71KB（35.5K x 16） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 2.5K x 16 |
| 电压 - 电源 (Vcc/Vdd)： | 3 V ~ 3.6 V |
| 数据转换器： | A/D 8x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 100-LQFP |
| 包装： | 托盘 |
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56F803 Technical Data, Rev. 16
12
Freescale Semiconductor
2.5 Interrupt and Program Control Signals
Table 2-7 Data Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
16
D0–D15
Input/O
utput
Tri-stated
Data Bus— D0–D15 specify the data for external Program or Data
memory accesses. D0–D15 are tri-stated when the external bus is
inactive. Internal pull-ups may be active.
Table 2-8 Bus Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
PS
Output
Tri-stated
Program Memory Select—PS is asserted low for external Program memory
access.
1
DS
Output
Tri-stated
Data Memory Select—DS is asserted low for external Data memory access.
1
WR
Output
Tri-stated
Write Enable—WR is asserted during external memory write cycles. When
WR is asserted low, pins D0–D15 become outputs and the device puts data
on the bus. When WR is deasserted high, the external data is latched inside
the external device. When WR is asserted, it qualifies the A0–A15, PS, and
DS pins. WR can be connected directly to the WE pin of a Static RAM.
1
RD
Output
Tri-stated
Read Enable—RD is asserted during external memory read cycles. When
RD is asserted low, pins D0–D15 become inputs and an external device is
enabled onto the device data bus. When RD is deasserted high, the external
data is latched inside the controller. When RD is asserted, it qualifies the
A0–A15, PS, and DS pins. RD can be connected directly to the OE pin of a
Static RAM or ROM.
Table 2-9 Interrupt and Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
IRQA
Input
(Schmitt)
Input
External Interrupt Request A—The IRQA input is a synchronized
external interrupt request indicating an external device is requesting
service. It can be programmed to be level-sensitive or
negative-edge- triggered.
1
IRQB
Input
(Schmitt)
Input
External Interrupt Request B—The IRQB input is an external
interrupt request indicating an external device is requesting service.
It can be programmed to be level-sensitive or
negative-edge-triggered.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DSP56F803BU80E | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor |
| DSP56F803BU80E | 制造商:Freescale Semiconductor 功能描述:DSP LQFP100 3.6V |
| DSP56F803E | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:16-bit Digital Signal Controllers |
| DSP56F803EVM | 功能描述:开发板和工具包 - 其他处理器 Evaluation Kit For DSP56F803 RoHS:否 制造商:Freescale Semiconductor 产品:Development Systems 工具用于评估:P3041 核心:e500mc 接口类型:I2C, SPI, USB 工作电源电压: |
| DSP56F803EVMUM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:56F803 Evaluation Module Hardware User＇s Manual |
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