参数资料
型号: DSPIC30F4013-30I/ML
厂商: Microchip Technology
文件页数: 141/153页
文件大小: 0K
描述: IC DSPIC MCU/DSP 48K 44QFN
产品培训模块: Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
标准包装: 45
系列: dsPIC™ 30F
核心处理器: dsPIC
芯体尺寸: 16-位
速度: 30 MIP
连通性: CAN,I²C,SPI,UART/USART
外围设备: AC'97,欠压检测/复位,I²S,POR,PWM,WDT
输入/输出数: 30
程序存储器容量: 48KB(16K x 24)
程序存储器类型: 闪存
EEPROM 大小: 1K x 8
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.5 V ~ 5.5 V
数据转换器: A/D 13x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-VQFN 裸露焊盘
包装: 管件
产品目录页面: 651 (CN2011-ZH PDF)
配用: XLT44QFN2-ND - SOCKET TRAN ICE 44QFN/40DIP
AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名称: DSPIC30F401330IML
dsPIC30F3014/4013
DS70138G-page 88
2010 Microchip Technology Inc.
13.5
Output Compare Operation During
CPU Sleep Mode
When the CPU enters Sleep mode, all internal clocks
are stopped. Therefore, when the CPU enters the
Sleep state, the output compare channel drives the pin
to the active state that was observed prior to entering
the CPU Sleep state.
For example, if the pin was high when the CPU entered
the Sleep state, the pin remains high. Likewise, if the
pin was low when the CPU entered the Sleep state, the
pin remains low. In either case, the output compare
module resumes operation when the device wakes up.
13.6
Output Compare Operation During
CPU Idle Mode
When the CPU enters the Idle mode, the output
compare module can operate with full functionality.
The output compare channel operates during the CPU
Idle mode if the OCSIDL bit (OCxCON<13>) is at logic
‘0’ and the selected time base (Timer2 or Timer3) is
enabled and the TSIDL bit of the selected timer is set
to logic ‘0’.
13.7
Output Compare Interrupts
The output compare channels have the ability to gener-
ate an interrupt on a compare match for whichever
Match mode has been selected.
For all modes, except the PWM mode, when a com-
pare event occurs, the respective interrupt flag (OCxIF)
is asserted and an interrupt is generated, if enabled.
The OCxIF bit is located in the corresponding IFSx reg-
ister and must be cleared in software. The interrupt is
enabled via the respective compare interrupt enable
(OCxIE) bit located in the corresponding IEC register.
For the PWM mode, when an event occurs, the respec-
tive Timer Interrupt Flag (T2IF or T3IF) is asserted and
an interrupt is generated, if enabled. The TxIF bit is
located in the IFS0 register and must be cleared in soft-
ware. The interrupt is enabled via the respective timer
interrupt enable bit (T2IE or T3IE) located in the IEC0
register. The output compare interrupt flag is never set
during the PWM mode of operation.
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