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型号： DSPIC30F4013-30I/ML
厂商： Microchip Technology
文件页数： 52/153页
文件大小： 0K
描述： IC DSPIC MCU/DSP 48K 44QFN
产品培训模块： Serial Communications using dsPIC30F CAN
Serial Communications using dsPIC30F I2C
Serial Communications using dsPIC30F SPI
Serial Communications using dsPIC30F UART
dsPIC30F 12 bit ADC - Part 2
dsPIC30F Addressing Modes - Part 1
dsPIC30F Architecture - Part 1
dsPIC30F DSP Engine & ALU
dsPIC30F Interrupts
dsPIC30F Motor Control PWM
dsPIC Timers
Asynchronous Stimulus
dsPIC30F Addressing Modes - Part 2
dsPIC30F Architecture - Part 2
dsPIC30F 12-bit ADC Part 1
标准包装： 45
系列： dsPIC™ 30F
核心处理器： dsPIC
芯体尺寸： 16-位
速度： 30 MIP
连通性： CAN，I²C，SPI，UART/USART
外围设备： AC'97，欠压检测/复位，I²S，POR，PWM，WDT
输入/输出数： 30
程序存储器容量： 48KB（16K x 24）
程序存储器类型： 闪存
EEPROM 大小： 1K x 8
RAM 容量： 2K x 8
电压 - 电源 (Vcc/Vdd)： 2.5 V ~ 5.5 V
数据转换器： A/D 13x12b
振荡器型： 内部
工作温度： -40°C ~ 85°C
封装/外壳： 44-VQFN 裸露焊盘
包装： 管件
产品目录页面： 651 (CN2011-ZH PDF)
配用： XLT44QFN2-ND - SOCKET TRAN ICE 44QFN/40DIP
AC164322-ND - MODULE SOCKET MPLAB PM3 28/44QFN
DV164005-ND - KIT ICD2 SIMPLE SUIT W/USB CABLE
其它名称： DSPIC30F401330IML
2010 Microchip Technology Inc.
DS70138G-page 145
dsPIC30F3014/4013
20.2.3
LP OSCILLATOR CONTROL
Enabling the LP oscillator is controlled with two
elements:
The current oscillator group bits, COSC<2:0>.
The LPOSCEN bit (OSCCON register).
The LP oscillator is on (even during Sleep mode) if
LPOSCEN = 1. The LP oscillator is the device clock if:
COSC<2:0> = 00 (LP selected as main osc.) and
LPOSCEN = 1
Keeping the LP oscillator on at all times allows for a fast
switch to the 32 kHz system clock for lower power
operation. Returning to the faster main oscillator still
requires a start-up time
20.2.4
PHASE LOCKED LOOP (PLL)
The PLL multiplies the clock which is generated by the
primary oscillator. The PLL is selectable to have either
gains of x4, x8 and x16. Input and output frequency
ranges are summarized in Table 20-3.
TABLE 20-3:
PLL FREQUENCY RANGE
The PLL features a lock output which is asserted when
the PLL enters a phase locked state. Should the loop
fall out of lock (e.g., due to noise), the lock signal is
rescinded. The state of this signal is reflected in the
read-only LOCK bit in the OSCCON register.
20.2.5
FAST RC OSCILLATOR (FRC)
The FRC oscillator is a fast (7.37 MHz ±2% nominal)
internal RC oscillator. This oscillator is intended to pro-
vide reasonable device operating speeds without the
use of an external crystal, ceramic resonator, or RC
network. The FRC oscillator can be used with the PLL
to obtain higher clock frequencies.
The dsPIC30F operates from the FRC oscillator when-
ever the current oscillator selection control bits in the
OSCCON register (OSCCON<14:12>) are set to ‘001’.
The
four-bit
field
specified
by
TUN<3:0>
(OSCTUN<3:0>) allows the user to tune the internal
fast RC oscillator (nominal 7.37 MHz). The user can
tune the FRC oscillator within a range of +10.5%
(840 kHz) and -12% (960 kHz) in steps of 1.50%
around the factory-calibrated setting (see Table 20-4).
If OSCCON<14:12> are set to ‘111’ and FPR<4:0> are
set to ‘00101’, ‘00110’ or ‘00111’, then a PLL
multiplier of 4, 8 or 16 (respectively) is applied.
TABLE 20-4:
FRC TUNING
20.2.6
LOW-POWER RC OSCILLATOR (LPRC)
The LPRC oscillator is a component of the Watchdog
Timer (WDT) and oscillates at a nominal frequency of
512 kHz. The LPRC oscillator is the clock source for
the Power-up Timer (PWRT) circuit, WDT and clock
monitor circuits. It may also be used to provide a low-
frequency clock source option for applications where
power consumption is critical and timing accuracy is
not required.
The LPRC oscillator is always enabled at a Power-on
Reset because it is the clock source for the PWRT.
After the PWRT expires, the LPRC oscillator remains
on if one of the following is TRUE:
The Fail-Safe Clock Monitor is enabled
The WDT is enabled
The LPRC oscillator is selected as the system
clock via the COSC<2:0> control bits in the
OSCCON register
If one of the above conditions is not true, the LPRC
shuts off after the PWRT expires.
FIN
PLL
Multiplier
FOUT
4 MHz-10 MHz
x4
16 MHz-40 MHz
4 MHz-10 MHz
x8
32 MHz-80 MHz
4 MHz-7.5 MHz
x16
64 MHz-120 MHz
Note:
OSCTUN functionality has been provided
to
help
customers
compensate
for
temperature effects on the FRC frequency
over a wide range of temperatures. The
tuning step size is an approximation and is
neither characterized nor tested.
Note:
When a 16x PLL is used, the FRC
frequency
must
not
be
tuned
to
a
frequency greater than 7.5 MHz.
TUN<3:0>
Bits
FRC Frequency
0111
+10.5%
0110
+9.0%
0101
+7.5%
0100
+6.0%
0011
+4.5%
0010
+3.0%
0001
+1.5%
0000
Center Frequency (oscillator is
running at calibrated frequency)
1111
-1.5%
1110
-3.0%
1101
-4.5%
1100
-6.0%
1011
-7.5%
1010
-9.0%
1001
-10.5%
1000
-12.0%
Note 1: OSC2 pin function is determined by the
Primary
Oscillator
mode
selection
(FPR<4:0>).
2: OSC1 pin cannot be used as an I/O pin
even if the secondary oscillator or an
internal clock source is selected at all
times.
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