E-1110 Core Functional Description
2-3
As shown in the block diagram (
Figure 2.1), the E-1110 core consists of
the following blocks:
Host Interface Module
Gigabit MAC
Gigabit MAC Flow Control Module
E-110 Flow Control Module1
Physical Interface Multiplexer
2.1.1 Host Interface Module
The Host Interface module provides an 8-bit, 125 MHz interface that
allows the host to communicate with the E-110 MAC core, the E-110
Flow Control module, and the Gigabit MAC. The Host Interface module
contains the required buffers and FIFOs to transfer data to and from the
E-110 core at 2.5 MHz or 25 MHz as well as to manage data transfers
to the Gigabit MAC at 125 MHz. The Host Interface module also contains
all the required multiplexing and demultiplexing logic for the interface
signals. In addition, the Host Interface module reads the remote
monitoring (RMON) vector from the E-110 MAC core and converts it into
a detailed RMON vector similar to the one the Gigabit MAC generates.
The Gigabit MAC has an 8-bit, 125 MHz interface. The Host Interface
module buffers the data transferred to and from the Gigabit MAC and
remaps the control interface protocol dened in the E-1110 packet
interface (start of packet, data valid, end of packet, and acknowledge).
The signals are then multiplexed with the related data and control signals
coming from the E-110. The result is that the host sees common start of
packet, data valid, end of packet, and acknowledge signals whether they
originate with the E-110 or the Gigabit MAC. The RMON vectors from
the E-110 core and the Gigabit MAC are also multiplexed into a single
thus provides the same look and feel for the data and packet transfer
control protocol for both the E-110 core and the Gigabit MAC.
The E-110 core transfers data to and from the Host Interface module
over an 8-bit interface using a 2.5 or 25 MHz MII clock. The receive data
1. Please refer to the E-110 documentation for more details on the operation of the E-110 Flow
Control module.