3-38
Signals
zeroes). The E-110 core continues sending this data pat-
tern as long as the host continues to assert the
E110_FC_FLS_CRS signal. If the E-110 core is already
sending out normal packet data on the MII, assertion of
the E110_FC_FLS_CRS pin only goes into effect after
the current transmission is completed. If the E-110 core
is already sending out a false carrier data pattern on the
MII, any transmit requests from the host are kept pending
until the E110_FC_FLS_CRS pin is deasserted. It is the
responsibility of the host to disable the jabber timer if the
E-110 core is being used in the 10BASE-T mode and if
the E110_FC_FLS_CRS pin is asserted for more than
20 ms. The E-110 core ignores collisions during
transmission of data while the E110_FC_FLS_CRS pin is
asserted. Standard management information related to
the Ethernet interface is not affected by the
E110_FC_FLS_CRS signal.
E110_CRCG
E-110 CRCG Output
Input
The E110_CRCG signal, when asserted, indicates that
the E110_CRCO[9:1] signals are valid. The E110_CRCG
signal, when deasserted, indicates that the
E110_CRCO[9:1] signals are not valid.
E110_CRCO[9:1]
E-110 CRCO[9:1]
Input
The E110_CRCO[9:1] signals reect the state of the
receive function FCS register after the rst six bytes of
the receive packet have been received. When the
destination address bits that are received in the frame
contain a multicast address, the E-110 core uses its
built-in FCS generator to compute a nine-bit polynomial
(the nine MSBs of the 32-bit FCS generator) from the
incoming address. The value of this polynomial can be
used as an index into an external multicast lter hash
table.
MII_RXD[3:0] MII Receive Nibble Data
Output
MII_RXD[3:0] consists of four data signals that the
E-1110 drives synchronously on the rising edge of the
MII_RCLK clock. For each MII_RCLK period in which
MII_RXDV is asserted, the E-1110 transfers four bits of
data over the MII_RXD[3:0] signals to the E-110 MAC.
MII_RXD[0] is the least signicant bit. When MII_RXDV