3-6
Signals
CRCO[8:0]
CRCO Output
Output
The CRCO[8:0] signals reect the state of the receive
function FCS register after the rst six bytes of a receive
packet have been examined. CRCO[8:0] reects the
9 MSBs of the 32-bit CRC computed on the destination
address of the received packet.The host interface can
then decide to reject or accept the packet.
MRX_BYTE7 Byte 7 Valid Indicator
Output
When asserted, MRX_BYTE7 indicates that the host can
now sample the MRX_BCO and MRX_MCO signals. This
signal is asserted on the seventh data byte after
MRX_SOP is asserted and it is valid for one clock cycle.
The host interface can then decide to reject or accept
broadcast packets.
3.2 Transmit Function Signals
The host communicates with the E-1110 Gigabit MAC transmit function
using the signals listed in this section. Signal direction is from the
perspective of the E-1110 core.
MTX_SOP
Transmit Start of Packet
Input
The host asserts MTX_SOP to request that the MAC
start frame transmission. When the MTX_SOP input
signal is asserted, the rst byte of frame data is present
on the MTX_DATA[7:0] input bus. Once asserted, the
MTX_SOP signal remains asserted until the MAC asserts
the MTX_ACK output signal. The host is then committed
to the transmission of at least part of a frame or a frame
fragment. If, after the assertion MTX_SOP, the host
desires to cancel the frame transmission request, it may
deassert the MTX_DVALID input signal while the
MTX_ACK output signal is asserted to cause a data
underrun abort condition. The MAC then asserts
MTX_ABORT, which requests the host to abort the
current transmit cycle.
In Gigabit mode, maintenance of maximum system
transmit performance, relative to the IEEE 802.3
minimum interframe gap (IFG), requires that the
MTX_SOP input signal be reasserted within a maximum
of six CLK125 cycles after the deassertion of the last