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参数资料
型号： EFM32TG210F32
厂商： Energy Micro
文件页数： 125/136页
文件大小： 0K
描述： MCU 32BIT 32KB FLASH 32-QFN
特色产品： EFM32 Tiny Gecko
标准包装： 1
系列： Tiny Gecko
核心处理器： ARM? Cortex?-M3
芯体尺寸： 32-位
速度： 32MHz
连通性： EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART
外围设备： 欠压检测/复位，DMA，POR，PWM，WDT
输入/输出数： 24
程序存储器容量： 32KB（32K x 8）
程序存储器类型： 闪存
RAM 容量： 4K x 8
电压 - 电源 (Vcc/Vdd)： 1.8 V ~ 3.8 V
数据转换器： A/D 4x12b，D/A 1x12b
振荡器型： 外部
工作温度： -40°C ~ 85°C
封装/外壳： 32-VQFN 裸露焊盘
包装： 标准包装
其它名称： 914-1034-6
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
89
www.energymicro.com
Address
Name
Type
Required
privilege
Reset value
Description
0XE000E200
-
0XE000E204
ISPR0-
ISPR1
RW
Privileged
0x00000000
Section 4.2.4 (p. 90)
0XE000E280
-
0XE000E284
ICPR0-
ICPR1
RW
Privileged
0x00000000
Section 4.2.5 (p. 91)
0xE000E300
-
0xE000E304
IABR0-
IABR1
RO
Privileged
0x00000000
Section 4.2.6 (p. 91)
0xE000E400
-
0xE000E400+4xm
IPR0-
IPRm
RW
Privileged
0x00000000
Section 4.2.7 (p. 92)
1
0xE000EF00
STIR
WO
Configurable
2
0x00000000
Section 4.2.8 (p. 93)
1m=(n-1)/4, where n denotes the number of interrupts given in Table 1.1 (p. 5) .
2See the register description for more information.
4.2.1 The CMSIS mapping of the Cortex-M3 NVIC registers
To improve software efficiency, the CMSIS simplifies the NVIC register presentation. In the CMSIS:
the Set-enable, Clear-enable, Set-pending, Clear-pending and Active Bit registers map to arrays of
32-bit integers, so that:
ISER[0] to ISER[1]corresponds to the registers ISER0-ISER1
ICER[0] to ICER[1]corresponds to the registers ICER0-ICER1
ISPR[0] to ISPR[1]corresponds to the registers ISPR0-ISPR1
ICPR[0] to ICPR[1]corresponds to the registers ICPR0-ICPR1
IABR[0] to IABR[1]corresponds to the registers IABR0-IABR1
the 8-bit fields of the Interrupt Priority Registers map to an array of 8-bit integers, so that the array
IP[0]
to IP[n-1] corresponds to the registers IPR0-IPRm (m=(n-1)/4, where n denotes the number
of interrupts given by Table 1.1 (p. 5) ), and the array entry IP[N] holds the interrupt priority for
interrupt N.
The CMSIS provides thread-safe code that gives atomic access to the Interrupt Priority Registers. For
more information see the description of the NVIC_SetPriority function in Section 4.2.10.1 (p. 94)
. Table 4.3 (p. 89) shows how the interrupts, or IRQ numbers, map onto the interrupt registers and
corresponding CMSIS variables that have one bit per interrupt.
Table 4.3. Mapping of interrupts to the interrupt variables
CMSIS array elements
1
Interrupts
Set-enable
Clear-enable
Set-pending
Clear-pending
Active Bit
0-31
ISER[0]
ICER[0]
ISPR[0]
ICPR[0]
IABR[0]
32-63
ISER[1]
ICER[1]
ISPR[1]
ICPR[1]
IABR[1]
1Each array element corresponds to a single NVIC register, for example the element ICER[1] corresponds to the ICER1 register.
4.2.2 Interrupt Set-enable Registers
The ISER0 and ISER1 registers enable interrupts, and show which interrupts are enabled. See:
the register summary in Table 4.2 (p. 88) for the register attributes
Table 4.3 (p. 89) for which interrupts are controlled by each register.
The bit assignments are:
SETENA bit s
31
0
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