参数资料
| 型号： | EFM32TG210F32 |
| 厂商： | Energy Micro |
| 文件页数： | 39/136页 |
| 文件大小： | 0K |
| 描述： | MCU 32BIT 32KB FLASH 32-QFN |
| 特色产品： | EFM32 Tiny Gecko |
| 标准包装： | 1 |
| 系列： | Tiny Gecko |
| 核心处理器： | ARM? Cortex?-M3 |
| 芯体尺寸： | 32-位 |
| 速度： | 32MHz |
| 连通性： | EBI/EMI，I²C，IrDA，智能卡，SPI，UART/USART |
| 外围设备： | 欠压检测/复位，DMA，POR，PWM，WDT |
| 输入/输出数： | 24 |
| 程序存储器容量： | 32KB（32K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 4K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 1.8 V ~ 3.8 V |
| 数据转换器： | A/D 4x12b，D/A 1x12b |
| 振荡器型： | 外部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 32-VQFN 裸露焊盘 |
| 包装： | 标准包装 |
| 其它名称： | 914-1034-6 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页当前第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页
...the world's most energy friendly microcontrollers
2011-02-04 - d0002_Rev1.00
133
www.energymicro.com
List of Tables
1.1. Cortex-M3 configuration in EFM32 series .................................................................................................... 5
2.1. Summary of processor mode, execution privilege level, and stack use options .................................................... 6
2.2. Core register set summary ....................................................................................................................... 7
2.3. PSR register combinations ....................................................................................................................... 9
2.4. APSR bit assignments ............................................................................................................................. 9
2.5. IPSR bit assignments ............................................................................................................................ 10
2.6. EPSR bit assignments ........................................................................................................................... 10
2.7. PRIMASK register bit assignments ........................................................................................................... 11
2.8. FAULTMASK register bit assignments ....................................................................................................... 12
2.9. BASEPRI register bit assignments ............................................................................................................ 12
2.10. CONTROL register bit assignments ........................................................................................................ 13
2.11. Memory access behavior ...................................................................................................................... 16
2.12. SRAM memory bit-banding regions ......................................................................................................... 18
2.13. Peripheral memory bit-banding regions .................................................................................................... 18
2.14. C compiler intrinsic functions for exclusive access instructions ..................................................................... 21
2.15. Properties of the different exception types ................................................................................................ 23
2.16. Exception return behavior ..................................................................................................................... 28
2.17. Faults ................................................................................................................................................ 28
2.18. Fault status and fault address registers ................................................................................................... 30
3.1. Cortex-M3 instructions ........................................................................................................................... 33
3.2. CMSIS intrinsic functions to generate some Cortex-M3 instructions ................................................................ 37
3.3. CMSIS intrinsic functions to access the special registers .............................................................................. 37
3.4. Condition code suffixes .......................................................................................................................... 44
3.5. Memory access instructions .................................................................................................................... 45
3.6. Offset ranges ...................................................................................................................................... 48
3.7. Offset ranges ....................................................................................................................................... 51
3.8. Data processing instructions .................................................................................................................... 56
3.9. Multiply and divide instructions ................................................................................................................ 66
3.10. Packing and unpacking instructions ........................................................................................................ 71
3.11. Branch and control instructions .............................................................................................................. 73
3.12. Branch ranges .................................................................................................................................... 74
3.13. Miscellaneous instructions ..................................................................................................................... 79
4.1. Core peripheral register regions ............................................................................................................... 88
4.2. NVIC register summary ......................................................................................................................... 88
4.3. Mapping of interrupts to the interrupt variables ........................................................................................... 89
4.4. ISER bit assignments ............................................................................................................................ 90
4.5. ICER bit assignments ............................................................................................................................ 90
4.6. ISPR bit assignments ............................................................................................................................ 91
4.7. ICPR bit assignments ............................................................................................................................ 91
4.8. IABR bit assignments ............................................................................................................................ 92
4.9. IPR bit assignments .............................................................................................................................. 92
4.10. STIR bit assignments ........................................................................................................................... 93
4.11. CMSIS functions for NVIC control ........................................................................................................... 94
4.12. Summary of the system control block registers ........................................................................................ 94
4.13. ACTLR bit assignments ........................................................................................................................ 95
4.14. CPUID register bit assignments ............................................................................................................ 96
4.15. ICSR bit assignments ........................................................................................................................... 97
4.16. VTOR bit assignments ........................................................................................................................ 99
4.17. AIRCR bit assignments ........................................................................................................................ 99
4.18. Priority grouping ................................................................................................................................ 100
4.19. SCR bit assignments ......................................................................................................................... 100
4.20. CCR bit assignments ........................................................................................................................ 101
4.21. System fault handler priority fields ........................................................................................................ 102
4.22. SHPR1 register bit assignments .......................................................................................................... 103
4.23. SHPR2 register bit assignments .......................................................................................................... 103
4.24. SHPR3 register bit assignments .......................................................................................................... 103
4.25. SHCSR bit assignments ...................................................................................................................... 104
4.26. MMFSR bit assignments ..................................................................................................................... 106
4.27. BFSR bit assignments ........................................................................................................................ 107
4.28. UFSR bit assignments ........................................................................................................................ 108
4.29. HFSR bit assignments ........................................................................................................................ 109
4.30. MMFAR bit assignments ..................................................................................................................... 110
4.31. BFAR bit assignments ........................................................................................................................ 110
4.32. System timer registers summary ........................................................................................................... 111
4.33. SysTick CTRL register bit assignments .................................................................................................. 111
4.34. LOAD register bit assignments ............................................................................................................. 112
4.35. VAL register bit assignments ............................................................................................................... 112
4.36. CALIB register bit assignments ............................................................................................................. 113
4.37. Memory attributes summary ................................................................................................................. 114
4.38. MPU registers summary ...................................................................................................................... 114
4.39. TYPE register bit assignments ............................................................................................................. 115
相关PDF资料 |
PDF描述 |
|---|---|
| MPC565CZP56 | IC MPU 32BIT IM FLASH 388-PBGA |
| C8051F587-IQ | IC 8051 MCU 96K FLASH 32-QFP |
| MC68HC11F1CFN2 | IC MCU 512 EEPROM 2MHZ 68-PLCC |
| MC68HC11F1CFN3 | IC MCU 512 EEPROM 3MHZ 68-PLCC |
| MC68HC11F1CFN4 | IC MCU 512 EEPROM 4MHZ 68-PLCC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| EFM32TG210F32-QFN32 | 制造商:Energy Micro AS 功能描述:TINY GECKO MCU - Tape and Reel 制造商:Energy Micro AS 功能描述:TINY GECKO MCU - Cut TR (SOS) 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 32QFN |
| EFM32TG210F32-QFN32T | 制造商:Energy Micro AS 功能描述:32 BIT ARM MPU, TINY GECKO - Trays |
| EFM32TG210F32-QFN32-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 32QFN |
| EFM32-TG210F32-SK | 功能描述:IC MICRO KIT GECKO 32QFN RoHS:是 类别:套件 >> 半导体产品 - IC 元件分类 系列:Tiny Gecko 其它有关文件:NXPLOGIC2-KIT-ND Contents 标准包装:1 系列:74AUP 套件类型:逻辑 值:180 件 - 18 种值各 10 件 包装:- 安装类型:表面贴装 包括封装:6-XSON，8-XSON，8-XQFN 产品目录页面:2653 (CN2011-ZH PDF) 工具箱内容:(10) 568-4391-1-ND - IC GATE MULT-FUNC CONFIG 6-XSON(10) 568-4390-1-ND - IC CONFIG MULT-FUNC GATE 6-XSON(10) 568-4389-1-ND - IC GATE DUAL FUNCTION 8-XSON(10) 568-4388-1-ND - IC GATE DUAL FUNCTION 8-XQFN(10) 568-4387-1-ND - IC F-F D-TYPE POS EDGE 8-XSON(10) 568-4386-1-ND - IC F-F D-TYPE POS EDGE 8-XQFN(10) 568-4385-1-ND - IC CONFIG MULTI-FUNC GATE 6-XSON(10) 568-4384-1-ND - IC EX-OR GATE 3-IN 6-XSON(10) 568-4383-1-ND - IC F-F D-TYPE POS EDGE 6-XSON(10) 568-4382-1-ND - IC LATCH D-TYPE 6-XSON更多... 其它名称:NXPLOGIC2-KIT |
| EFM32TG210F32-T | 制造商:Energy Micro AS 功能描述:IC MCU 32BIT 32KB FLASH 32QFN |
发布紧急采购，3分钟左右您将得到回复。